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-rw-r--r--src/amd/addrlib/amdgpu_asic_addr.h2
-rw-r--r--src/amd/addrlib/gfx9/gfx9addrlib.cpp3
-rw-r--r--src/amd/addrlib/gfx9/gfx9addrlib.h1
3 files changed, 5 insertions, 1 deletions
diff --git a/src/amd/addrlib/amdgpu_asic_addr.h b/src/amd/addrlib/amdgpu_asic_addr.h
index b4b8aecd42d..e5838d42a3c 100644
--- a/src/amd/addrlib/amdgpu_asic_addr.h
+++ b/src/amd/addrlib/amdgpu_asic_addr.h
@@ -87,6 +87,7 @@
#define AMDGPU_VEGA10_RANGE 0x01, 0x14
#define AMDGPU_VEGA12_RANGE 0x14, 0x28
+#define AMDGPU_VEGA20_RANGE 0x28, 0xFF
#define AMDGPU_RAVEN_RANGE 0x01, 0x81
@@ -128,6 +129,7 @@
#define ASICREV_IS_VEGA10_P(r) ASICREV_IS(r, VEGA10)
#define ASICREV_IS_VEGA12_P(r) ASICREV_IS(r, VEGA12)
#define ASICREV_IS_VEGA12_p(r) ASICREV_IS(r, VEGA12)
+#define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20)
#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.cpp b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
index b88d3243228..ef86c3bc7b5 100644
--- a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
+++ b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
@@ -1230,6 +1230,7 @@ BOOL_32 Gfx9Lib::HwlInitGlobalParams(
{
ADDR_ASSERT(m_settings.isVega10 == FALSE);
ADDR_ASSERT(m_settings.isRaven == FALSE);
+ ADDR_ASSERT(m_settings.isVega20 == FALSE);
if (m_settings.isVega12)
{
@@ -1273,7 +1274,7 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
m_settings.isArcticIsland = 1;
m_settings.isVega10 = ASICREV_IS_VEGA10_P(uChipRevision);
m_settings.isVega12 = ASICREV_IS_VEGA12_P(uChipRevision);
-
+ m_settings.isVega20 = ASICREV_IS_VEGA20_P(uChipRevision);
m_settings.isDce12 = 1;
if (m_settings.isVega10 == 0)
diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.h b/src/amd/addrlib/gfx9/gfx9addrlib.h
index 7c61a40880e..cf56507964c 100644
--- a/src/amd/addrlib/gfx9/gfx9addrlib.h
+++ b/src/amd/addrlib/gfx9/gfx9addrlib.h
@@ -56,6 +56,7 @@ struct Gfx9ChipSettings
UINT_32 isVega10 : 1;
UINT_32 isRaven : 1;
UINT_32 isVega12 : 1;
+ UINT_32 isVega20 : 1;
// Display engine IP version name
UINT_32 isDce12 : 1;