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-rw-r--r--src/amd/addrlib/addrinterface.cpp4
-rw-r--r--src/amd/addrlib/gfx9/gfx9addrlib.cpp10
-rw-r--r--src/amd/addrlib/gfx9/rbmap.cpp10
-rw-r--r--src/amd/addrlib/r800/egbaddrlib.cpp6
4 files changed, 15 insertions, 15 deletions
diff --git a/src/amd/addrlib/addrinterface.cpp b/src/amd/addrlib/addrinterface.cpp
index 12985fc37b6..6a0c330dcc5 100644
--- a/src/amd/addrlib/addrinterface.cpp
+++ b/src/amd/addrlib/addrinterface.cpp
@@ -832,7 +832,7 @@ BOOL_32 ADDR_API ElemGetExportNorm(
Addr::Lib* pLib = Lib::GetLib(hLib);
BOOL_32 enabled = FALSE;
- ADDR_E_RETURNCODE returnCode = ADDR_OK;
+ //ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (pLib != NULL)
{
@@ -840,7 +840,7 @@ BOOL_32 ADDR_API ElemGetExportNorm(
}
else
{
- returnCode = ADDR_ERROR;
+ //returnCode = ADDR_ERROR;
}
ADDR_ASSERT(returnCode == ADDR_OK);
diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.cpp b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
index c6e2b9720e8..fce0c000be9 100644
--- a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
+++ b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
@@ -1467,7 +1467,7 @@ VOID Gfx9Lib::GetMetaEquation(
{
UINT_32 numPipeTotalLog2 = GetPipeLog2ForMetaAddressing(metaFlag.pipeAligned, swizzleMode);
UINT_32 pipeInterleaveLog2 = m_pipeInterleaveLog2;
- UINT_32 blockSizeLog2 = GetBlockSizeLog2(swizzleMode);
+ //UINT_32 blockSizeLog2 = GetBlockSizeLog2(swizzleMode);
// Get the correct data address and rb equation
CoordEq dataEq;
@@ -1921,8 +1921,8 @@ UINT_32 Gfx9Lib::HwlGetEquationIndex(
pMipInfo->mipOffsetZPixel = 0;
pMipInfo->postSwizzleOffset = 0;
- static const UINT_32 Prt_Xor_Gap =
- static_cast<UINT_32>(ADDR_SW_64KB_Z_T) - static_cast<UINT_32>(ADDR_SW_64KB_Z);
+ /*static const UINT_32 Prt_Xor_Gap =
+ static_cast<UINT_32>(ADDR_SW_64KB_Z_T) - static_cast<UINT_32>(ADDR_SW_64KB_Z);*/
for (UINT_32 i = 1; i < numMipLevels; i++)
{
@@ -2159,7 +2159,7 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlComputeBlock256Equation(
// Post validation
if (ret == ADDR_OK)
{
- Dim2d microBlockDim = Block256b[elementBytesLog2];
+ //Dim2d microBlockDim = Block256b[elementBytesLog2];
ADDR_ASSERT((2u << GetMaxValidChannelIndex(pEquation->addr, 8, 0)) ==
(microBlockDim.w * (1 << elementBytesLog2)));
ADDR_ASSERT((2u << GetMaxValidChannelIndex(pEquation->addr, 8, 1)) == microBlockDim.h);
@@ -2605,7 +2605,7 @@ BOOL_32 Gfx9Lib::HwlIsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_I
{
BOOL_32 support = FALSE;
- const AddrResourceType resourceType = pIn->resourceType;
+ //const AddrResourceType resourceType = pIn->resourceType;
const AddrSwizzleMode swizzleMode = pIn->swizzleMode;
if (m_settings.isDce12)
diff --git a/src/amd/addrlib/gfx9/rbmap.cpp b/src/amd/addrlib/gfx9/rbmap.cpp
index 470b9f37d7e..789140d7c0e 100644
--- a/src/amd/addrlib/gfx9/rbmap.cpp
+++ b/src/amd/addrlib/gfx9/rbmap.cpp
@@ -47,7 +47,7 @@ VOID RB_MAP::Get_Comp_Block_Screen_Space( CoordEq& addr, int bytes_log2, int* w,
if( h ) *h = 0;
if( d ) *d = 0;
for( n=0; n<bytes_log2; n++ ) { // go up to the bytes_log2 bit
- for( i=0; i<addr[n].getsize(); i++ ) {
+ for( i=0; (unsigned)i<addr[n].getsize(); i++ ) {
char dim = addr[n][i].getdim();
int ord = addr[n][i].getord();
if( w && dim == 'x' && ord >= *w ) *w = ord+1;
@@ -685,7 +685,7 @@ RB_MAP::get_meta_eq( CoordEq& metaaddr,
bool data_linear = ( data_type == DATA_COLOR1D || data_type == DATA_COLOR2D_LINEAR );
bool is_color = ( data_linear || data_type == DATA_COLOR2D || data_type == DATA_COLOR3D_S || data_type == DATA_COLOR3D_Z || data_type == DATA_COLOR3D_D_NOT_USED );
- bool is3d = ( data_type == DATA_COLOR3D_S || data_type == DATA_COLOR3D_Z || data_type == DATA_COLOR3D_D_NOT_USED );
+ //bool is3d = ( data_type == DATA_COLOR3D_S || data_type == DATA_COLOR3D_Z || data_type == DATA_COLOR3D_D_NOT_USED );
bool is_thick = ( data_type == DATA_COLOR3D_S || data_type == DATA_COLOR3D_Z );
bool is_fmask = (data_type == DATA_FMASK);
@@ -933,7 +933,7 @@ RB_MAP::get_meta_eq( CoordEq& metaaddr,
if( cur_rbeq[j].remove( co ) ) {
// if we actually removed something from this bit, then add the remaining
// channel bits, as these can be removed for this bit
- for( k=0; k<pipe_equation[i].getsize(); k++ ) {
+ for( k=0; (unsigned)k<pipe_equation[i].getsize(); k++ ) {
if( pipe_equation[i][k] != co ) {
cur_rbeq[j].add( pipe_equation[i][k] );
}
@@ -962,7 +962,7 @@ RB_MAP::get_meta_eq( CoordEq& metaaddr,
if( cur_rbeq[j].remove( co ) ) {
// if we actually removed something from this bit, then add the remaining
// rb bits, as these can be removed for this bit
- for( k=0; k<cur_rbeq[i].getsize(); k++ ) {
+ for( k=0; (unsigned)k<cur_rbeq[i].getsize(); k++ ) {
if( cur_rbeq[i][k] != co ) {
cur_rbeq[j].add( cur_rbeq[i][k] );
}
@@ -1072,7 +1072,7 @@ RB_MAP::get_meta_addr_calc( int x, int y, int z, int s,
CoordEq metaaddr;
- bool se_affinity_enable = false;
+ //bool se_affinity_enable = false;
//int max_pipe_bytes = std::max(1<<num_pipes_log2 * 1<<pipe_interleave_log2, 1024 * 1<<log2_element_bytes);
//int max_banks_samples = std::max(1<<num_banks_log2, 1<<num_samples_log2);
//int block_size_log2 = max(4096, max_pipe_bytes * max_bank_samples * 1<<num_ses_log2);
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index 0cd27ada070..03f3a3146e4 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -978,7 +978,7 @@ BOOL_32 EgBasedLib::SanityCheckMacroTiled(
) const
{
BOOL_32 valid = TRUE;
- UINT_32 numPipes = HwlGetPipes(pTileInfo);
+ //UINT_32 numPipes = HwlGetPipes(pTileInfo);
switch (pTileInfo->banks)
{
@@ -4748,7 +4748,7 @@ UINT_64 EgBasedLib::HwlGetSizeAdjustmentMicroTiled(
) const
{
UINT_64 logicalSliceSize;
- UINT_64 physicalSliceSize;
+ //UINT_64 physicalSliceSize;
UINT_32 pitch = *pPitch;
UINT_32 height = *pHeight;
@@ -4757,7 +4757,7 @@ UINT_64 EgBasedLib::HwlGetSizeAdjustmentMicroTiled(
logicalSliceSize = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples);
// Physical slice: multiplied by thickness
- physicalSliceSize = logicalSliceSize * thickness;
+ //physicalSliceSize = logicalSliceSize * thickness;
//
// R800 will always pad physical slice size to baseAlign which is pipe_interleave_bytes
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-17 23:28:56 +0000