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-rw-r--r--src/amd/addrlib/r800/egbaddrlib.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index 03f3a3146e4..0cd27ada070 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -978,7 +978,7 @@ BOOL_32 EgBasedLib::SanityCheckMacroTiled(
) const
{
BOOL_32 valid = TRUE;
- //UINT_32 numPipes = HwlGetPipes(pTileInfo);
+ UINT_32 numPipes = HwlGetPipes(pTileInfo);
switch (pTileInfo->banks)
{
@@ -4748,7 +4748,7 @@ UINT_64 EgBasedLib::HwlGetSizeAdjustmentMicroTiled(
) const
{
UINT_64 logicalSliceSize;
- //UINT_64 physicalSliceSize;
+ UINT_64 physicalSliceSize;
UINT_32 pitch = *pPitch;
UINT_32 height = *pHeight;
@@ -4757,7 +4757,7 @@ UINT_64 EgBasedLib::HwlGetSizeAdjustmentMicroTiled(
logicalSliceSize = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples);
// Physical slice: multiplied by thickness
- //physicalSliceSize = logicalSliceSize * thickness;
+ physicalSliceSize = logicalSliceSize * thickness;
//
// R800 will always pad physical slice size to baseAlign which is pipe_interleave_bytes