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-rw-r--r--src/mesa/drivers/dri/r300/r300_cmdbuf.c56
-rw-r--r--src/mesa/drivers/dri/r300/r300_cmdbuf.h2
-rw-r--r--src/mesa/drivers/dri/r300/r300_ioctl.c9
-rw-r--r--src/mesa/drivers/dri/r300/r300_render.c8
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_cs_legacy.c20
5 files changed, 33 insertions, 62 deletions
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index ed94520aba2..4eac5183b2f 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -341,14 +341,14 @@ static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom)
} else if (!t) {
OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
} else {
- if (t->bo) {
- OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
- RADEON_GEM_DOMAIN_VRAM, 0, 0);
- } else {
- OUT_BATCH(t->override_offset);
- }
+ if (t->bo) {
+ OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
+ RADEON_GEM_DOMAIN_VRAM, 0, 0);
+ } else {
+ OUT_BATCH(t->override_offset);
+ }
}
- END_BATCH();
+ END_BATCH();
}
}
}
@@ -361,9 +361,9 @@ static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom)
GLframebuffer *fb = r300->radeon.dri.drawable->driverPrivate;
rrb = r300->radeon.state.color.rrb;
- if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
- rrb = fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
- }
+ if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
+ rrb = fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+ }
if (!rrb || !rrb->bo) {
fprintf(stderr, "no rrb\n");
return;
@@ -397,13 +397,13 @@ static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom)
return;
zbpitch = (rrb->pitch / rrb->cpp);
- if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
- zbpitch |= R300_DEPTHMACROTILE_ENABLE;
- }
- if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
- zbpitch |= R300_DEPTHMICROTILE_TILED;
- }
-
+ if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
+ zbpitch |= R300_DEPTHMACROTILE_ENABLE;
+ }
+ if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
+ zbpitch |= R300_DEPTHMICROTILE_TILED;
+ }
+
BEGIN_BATCH(4);
OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
@@ -688,43 +688,43 @@ void r300InitCmdBuf(r300ContextPtr r300)
ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
r300->hw.vpi.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
- r300->hw.vpi.emit = emit_vpu;
+ r300->hw.vpi.emit = emit_vpu;
if (is_r500) {
ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
r300->hw.vpp.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
- r300->hw.vpp.emit = emit_vpu;
+ r300->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
r300->hw.vps.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
- r300->hw.vps.emit = emit_vpu;
+ r300->hw.vps.emit = emit_vpu;
for (i = 0; i < 6; i++) {
- ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
- r300->hw.vpucp[i].cmd[0] =
- cmdvpu(r300->radeon.radeonScreen,
+ ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
+ r300->hw.vpucp[i].cmd[0] =
+ cmdvpu(r300->radeon.radeonScreen,
R500_PVS_UCP_START + i, 1);
- r300->hw.vpucp[i].emit = emit_vpu;
+ r300->hw.vpucp[i].emit = emit_vpu;
}
} else {
ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
r300->hw.vpp.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
- r300->hw.vpp.emit = emit_vpu;
+ r300->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
r300->hw.vps.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
- r300->hw.vps.emit = emit_vpu;
+ r300->hw.vps.emit = emit_vpu;
for (i = 0; i < 6; i++) {
ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
r300->hw.vpucp[i].cmd[0] =
cmdvpu(r300->radeon.radeonScreen,
- R300_PVS_UCP_START + i, 1);
- r300->hw.vpucp[i].emit = emit_vpu;
+ R300_PVS_UCP_START + i, 1);
+ r300->hw.vpucp[i].emit = emit_vpu;
}
}
}
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.h b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
index 95701b49b43..bb7e0bf2960 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.h
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.h
@@ -93,8 +93,6 @@ void r300BeginBatch(r300ContextPtr r300,
radeon_cs_write_dword(b_l_r300->cmdbuf.cs, offset);\
radeon_cs_write_reloc(b_l_r300->cmdbuf.cs, \
bo, \
- offset, \
- (bo)->size, \
rd, \
wd, \
flags);\
diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index 0cf084bde54..6d7b191b24d 100644
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -499,9 +499,9 @@ static void r300EmitClearState(GLcontext * ctx)
OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
END_BATCH();
- vpu.check = check_vpu;
- vpu.cmd = _cmd;
- vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
+ vpu.check = check_vpu;
+ vpu.cmd = _cmd;
+ vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE,
0, 0xf, PVS_DST_REG_OUT);
@@ -520,6 +520,7 @@ static void r300EmitClearState(GLcontext * ctx)
vpu.cmd[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X,
PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z,
PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT,
+
VSF_FLAG_NONE);
vpu.cmd[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0,
PVS_SRC_SELECT_FORCE_0,
@@ -527,7 +528,7 @@ static void r300EmitClearState(GLcontext * ctx)
PVS_SRC_SELECT_FORCE_0,
PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
vpu.cmd[8] = 0x0;
- emit_vpu(r300, &vpu);
+ emit_vpu(r300, &vpu);
}
}
diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c
index dd9da80fd01..ccc00b381fa 100644
--- a/src/mesa/drivers/dri/r300/r300_render.c
+++ b/src/mesa/drivers/dri/r300/r300_render.c
@@ -214,8 +214,6 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type)
OUT_BATCH(vertex_count);
radeon_cs_write_reloc(rmesa->cmdbuf.cs,
rmesa->state.elt_dma_bo,
- 0,
- rmesa->state.elt_dma_bo->size,
RADEON_GEM_DOMAIN_GTT, 0, 0);
}
END_BATCH();
@@ -299,16 +297,12 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
offset * 4 * rmesa->state.aos[i + 0].stride;
radeon_cs_write_reloc(rmesa->cmdbuf.cs,
rmesa->state.aos[i+0].bo,
- voffset,
- rmesa->state.aos[i+0].bo->size,
RADEON_GEM_DOMAIN_GTT,
0, 0);
voffset = rmesa->state.aos[i + 1].offset +
offset * 4 * rmesa->state.aos[i + 1].stride;
radeon_cs_write_reloc(rmesa->cmdbuf.cs,
rmesa->state.aos[i+1].bo,
- voffset,
- rmesa->state.aos[i+1].bo->size,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
@@ -317,8 +311,6 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
offset * 4 * rmesa->state.aos[nr - 1].stride;
radeon_cs_write_reloc(rmesa->cmdbuf.cs,
rmesa->state.aos[nr-1].bo,
- voffset,
- rmesa->state.aos[nr-1].bo->size,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
index 20956ff5c7b..11b9f89ca7d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
+++ b/src/mesa/drivers/dri/radeon/radeon_cs_legacy.c
@@ -94,8 +94,6 @@ static int cs_write_dword(struct radeon_cs *cs, uint32_t dword)
static int cs_write_reloc(struct radeon_cs *cs,
struct radeon_bo *bo,
- uint32_t start_offset,
- uint32_t end_offset,
uint32_t read_domain,
uint32_t write_domain,
uint32_t flags)
@@ -117,25 +115,11 @@ static int cs_write_reloc(struct radeon_cs *cs,
if (write_domain == RADEON_GEM_DOMAIN_CPU) {
return -EINVAL;
}
- /* check reloc window */
- if (end_offset > bo->size) {
- return -EINVAL;
- }
- if (start_offset > end_offset) {
- return -EINVAL;
- }
/* check if bo is already referenced */
for(i = 0; i < cs->crelocs; i++) {
uint32_t *indices;
if (relocs[i].base.bo->handle == bo->handle) {
- /* update start and end offset */
- if (start_offset < relocs[i].base.start_offset) {
- relocs[i].base.start_offset = start_offset;
- }
- if (end_offset > relocs[i].base.end_offset) {
- relocs[i].base.end_offset = end_offset;
- }
/* Check domains must be in read or write. As we check already
* checked that in argument one of the read or write domain was
* set we only need to check that if previous reloc as the read
@@ -172,8 +156,6 @@ static int cs_write_reloc(struct radeon_cs *cs,
}
cs->relocs = relocs;
relocs[cs->crelocs].base.bo = bo;
- relocs[cs->crelocs].base.start_offset = start_offset;
- relocs[cs->crelocs].base.end_offset = end_offset;
relocs[cs->crelocs].base.read_domain = read_domain;
relocs[cs->crelocs].base.write_domain = write_domain;
relocs[cs->crelocs].base.flags = flags;
@@ -249,8 +231,6 @@ static int cs_process_relocs(struct radeon_cs *cs)
for (j = 0; j < relocs[i].cindices; j++) {
uint32_t soffset, eoffset;
- soffset = relocs[i].base.start_offset;
- eoffset = relocs[i].base.end_offset;
r = radeon_bo_legacy_validate(relocs[i].base.bo,
&soffset, &eoffset);
if (r) {
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-01 23:11:02 +0000