diff options
| -rw-r--r-- | src/gallium/drivers/freedreno/Makefile.sources | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_blitter.c | 448 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_blitter.h | 36 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_context.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_format.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/freedreno_screen.c | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/freedreno_util.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/meson.build | 2 |
8 files changed, 498 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/Makefile.sources b/src/gallium/drivers/freedreno/Makefile.sources index e6147151c6b..447a6f990e0 100644 --- a/src/gallium/drivers/freedreno/Makefile.sources +++ b/src/gallium/drivers/freedreno/Makefile.sources @@ -128,6 +128,8 @@ a5xx_SOURCES := \ a5xx/a5xx.xml.h \ a5xx/fd5_blend.c \ a5xx/fd5_blend.h \ + a5xx/fd5_blitter.c \ + a5xx/fd5_blitter.h \ a5xx/fd5_compute.c \ a5xx/fd5_compute.h \ a5xx/fd5_context.c \ diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c b/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c new file mode 100644 index 00000000000..5769b7eb8f3 --- /dev/null +++ b/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c @@ -0,0 +1,448 @@ +/* + * Copyright (C) 2017 Rob Clark <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark <[email protected]> + */ + +#include "freedreno_blitter.h" +#include "freedreno_resource.h" + +#include "fd5_blitter.h" +#include "fd5_format.h" +#include "fd5_emit.h" + +/* Make sure none of the requested dimensions extend beyond the size of the + * resource. Not entirely sure why this happens, but sometimes it does, and + * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases + * back to u_blitter + */ +static bool +ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl) +{ + return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) && + (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) && + (b->z >= 0) && (b->z + b->depth <= u_minify(r->depth0, lvl)); +} + +/* Not sure if format restrictions differ for src and dst, or if + * they only matter when src fmt != dst fmt.. but there appear to + * be *some* limitations so let's just start blacklisting stuff that + * piglit complains about + */ +static bool +ok_format(enum pipe_format fmt) +{ + switch (fmt) { + case PIPE_FORMAT_R10G10B10A2_SSCALED: + case PIPE_FORMAT_R10G10B10A2_SNORM: + case PIPE_FORMAT_B10G10R10A2_USCALED: + case PIPE_FORMAT_B10G10R10A2_SSCALED: + case PIPE_FORMAT_B10G10R10A2_SNORM: + case PIPE_FORMAT_R10G10B10A2_UNORM: + case PIPE_FORMAT_R10G10B10A2_USCALED: + case PIPE_FORMAT_B10G10R10A2_UNORM: + case PIPE_FORMAT_R10SG10SB10SA2U_NORM: + case PIPE_FORMAT_B10G10R10A2_UINT: + case PIPE_FORMAT_R10G10B10A2_UINT: + return false; + default: + return true; + } +} + +static bool +can_do_blit(const struct pipe_blit_info *info) +{ + /* I think we can do scaling, but not in z dimension since that would + * require blending.. + */ + if (info->dst.box.depth != info->src.box.depth) + return false; + + if (!ok_format(info->dst.format)) + return false; + + if (!ok_format(info->src.format)) + return false; + + /* until we figure out a few more registers: */ + if ((info->dst.box.width != info->src.box.width) || + (info->dst.box.height != info->src.box.height)) + return false; + + /* src box can be inverted, which we don't support.. dst box cannot: */ + if ((info->src.box.width < 0) || (info->src.box.height < 0)) + return false; + + if (!ok_dims(info->src.resource, &info->src.box, info->src.level)) + return false; + + if (!ok_dims(info->dst.resource, &info->dst.box, info->dst.level)) + return false; + + debug_assert(info->dst.box.width >= 0); + debug_assert(info->dst.box.height >= 0); + debug_assert(info->dst.box.depth >= 0); + + if (info->dst.resource->nr_samples + info->src.resource->nr_samples) + return false; + + if (info->scissor_enable) + return false; + + if (info->window_rectangle_include) + return false; + + if (info->render_condition_enable) + return false; + + if (info->alpha_blend) + return false; + + if (info->filter != PIPE_TEX_FILTER_NEAREST) + return false; + + if (info->mask != util_format_get_mask(info->src.format)) + return false; + + if (info->mask != util_format_get_mask(info->dst.format)) + return false; + + if (util_format_is_compressed(info->dst.format)) + return false; + + if (util_format_is_compressed(info->src.format)) + return false; + + return true; +} + +static void +emit_setup(struct fd_ringbuffer *ring) +{ + OUT_PKT7(ring, CP_EVENT_WRITE, 1); + OUT_RING(ring, LRZ_FLUSH); + + OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1); + OUT_RING(ring, 0x0); + + OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1); + OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */ + + OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1); + OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */ + + /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */ + OUT_WFI5(ring); + OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1); + OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */ + + OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1); + OUT_RING(ring, 0x00000008); + + OUT_PKT4(ring, REG_A5XX_UNKNOWN_2100, 1); + OUT_RING(ring, 0x86000000); /* UNKNOWN_2100 */ + + OUT_PKT4(ring, REG_A5XX_UNKNOWN_2180, 1); + OUT_RING(ring, 0x86000000); /* UNKNOWN_2180 */ + + OUT_PKT4(ring, REG_A5XX_UNKNOWN_2184, 1); + OUT_RING(ring, 0x00000009); /* UNKNOWN_2184 */ + + OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1); + OUT_RING(ring, A5XX_RB_CNTL_BYPASS); + + OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1); + OUT_RING(ring, 0x00000004); /* RB_MODE_CNTL */ + + OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1); + OUT_RING(ring, 0x0000000c); /* SP_MODE_CNTL */ + + OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1); + OUT_RING(ring, 0x00000344); /* TPL1_MODE_CNTL */ + + OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1); + OUT_RING(ring, 0x00000002); /* HLSQ_MODE_CNTL */ + + OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1); + OUT_RING(ring, 0x00000181); /* GRAS_CL_CNTL */ +} + +/* buffers need to be handled specially since x/width can exceed the bounds + * supported by hw.. if necessary decompose into (potentially) two 2D blits + */ +static void +emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info) +{ + const struct pipe_box *sbox = &info->src.box; + const struct pipe_box *dbox = &info->dst.box; + struct fd_resource *src, *dst; + unsigned sshift, dshift; + + src = fd_resource(info->src.resource); + dst = fd_resource(info->dst.resource); + + debug_assert(src->cpp == 1); + debug_assert(dst->cpp == 1); + debug_assert(info->src.resource->format == info->dst.resource->format); + debug_assert((sbox->y == 0) && (sbox->height == 1)); + debug_assert((dbox->y == 0) && (dbox->height == 1)); + debug_assert((sbox->z == 0) && (sbox->depth == 1)); + debug_assert((dbox->z == 0) && (dbox->depth == 1)); + debug_assert(sbox->width == dbox->width); + debug_assert(info->src.level == 0); + debug_assert(info->dst.level == 0); + + /* + * Buffers can have dimensions bigger than max width, remap into + * multiple 1d blits to fit within max dimension + * + * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which + * seems to prevent overfetch related faults. Not quite sure what + * the deal is there. + * + * Low 6 bits of SRC/DST addresses need to be zero (ie. address + * aligned to 64) so we need to shift src/dst x1/x2 to make up the + * difference. On top of already splitting up the blit so width + * isn't > 16k. + * + * We perhaps could do a bit better, if src and dst are aligned but + * in the worst case this means we have to split the copy up into + * 16k (0x4000) minus 64 (0x40). + */ + + sshift = sbox->x & 0x3f; + dshift = dbox->x & 0x3f; + + for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) { + unsigned soff, doff, w, p; + + soff = (sbox->x + off) & ~0x3f; + doff = (dbox->x + off) & ~0x3f; + + w = MIN2(sbox->width - off, (0x4000 - 0x40)); + p = align(w, 64); + + debug_assert((soff + w) <= fd_bo_size(src->bo)); + debug_assert((doff + w) <= fd_bo_size(dst->bo)); + + OUT_PKT7(ring, CP_SET_RENDER_MODE, 1); + OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(BLIT2D)); + + /* + * Emit source: + */ + OUT_PKT4(ring, REG_A5XX_RB_2D_SRC_INFO, 9); + OUT_RING(ring, A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(RB5_R8_UNORM) | + A5XX_RB_2D_SRC_INFO_COLOR_SWAP(WZYX)); + OUT_RELOC(ring, src->bo, soff, 0, 0); /* RB_2D_SRC_LO/HI */ + OUT_RING(ring, A5XX_RB_2D_SRC_SIZE_PITCH(p) | + A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(128)); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + + OUT_PKT4(ring, REG_A5XX_GRAS_2D_SRC_INFO, 1); + OUT_RING(ring, A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(RB5_R8_UNORM) | + A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(WZYX)); + + /* + * Emit destination: + */ + OUT_PKT4(ring, REG_A5XX_RB_2D_DST_INFO, 9); + OUT_RING(ring, A5XX_RB_2D_DST_INFO_COLOR_FORMAT(RB5_R8_UNORM) | + A5XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX)); + OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */ + OUT_RING(ring, A5XX_RB_2D_DST_SIZE_PITCH(p) | + A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(128)); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + + OUT_PKT4(ring, REG_A5XX_GRAS_2D_DST_INFO, 1); + OUT_RING(ring, A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(RB5_R8_UNORM) | + A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(WZYX)); + + /* + * Blit command: + */ + OUT_PKT7(ring, CP_BLIT, 5); + OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_COPY)); + OUT_RING(ring, CP_BLIT_1_SRC_X1(sshift) | CP_BLIT_1_SRC_Y1(0)); + OUT_RING(ring, CP_BLIT_2_SRC_X2(sshift+w-1) | CP_BLIT_2_SRC_Y2(0)); + OUT_RING(ring, CP_BLIT_3_DST_X1(dshift) | CP_BLIT_3_DST_Y1(0)); + OUT_RING(ring, CP_BLIT_4_DST_X2(dshift+w-1) | CP_BLIT_4_DST_Y2(0)); + + OUT_PKT7(ring, CP_SET_RENDER_MODE, 1); + OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(END2D)); + + OUT_WFI5(ring); + } +} + +static void +emit_blit(struct fd_ringbuffer *ring, const struct pipe_blit_info *info) +{ + const struct pipe_box *sbox = &info->src.box; + const struct pipe_box *dbox = &info->dst.box; + struct fd_resource *src, *dst; + struct fd_resource_slice *sslice, *dslice; + enum a5xx_color_fmt sfmt, dfmt; + enum a3xx_color_swap sswap, dswap; + unsigned ssize, dsize, spitch, dpitch; + unsigned sx1, sy1, sx2, sy2; + unsigned dx1, dy1, dx2, dy2; + + src = fd_resource(info->src.resource); + dst = fd_resource(info->dst.resource); + + sslice = fd_resource_slice(src, info->src.level); + dslice = fd_resource_slice(dst, info->dst.level); + + sfmt = fd5_pipe2color(info->src.format); + dfmt = fd5_pipe2color(info->dst.format); + + sswap = fd5_pipe2swap(info->src.format); + dswap = fd5_pipe2swap(info->dst.format); + + spitch = sslice->pitch * src->cpp; + dpitch = dslice->pitch * dst->cpp; + + sx1 = sbox->x; + sy1 = sbox->y; + sx2 = sbox->x + sbox->width - 1; + sy2 = sbox->y + sbox->height - 1; + + dx1 = dbox->x; + dy1 = dbox->y; + dx2 = dbox->x + dbox->width - 1; + dy2 = dbox->y + dbox->height - 1; + + if (info->src.resource->target == PIPE_TEXTURE_3D) + ssize = sslice->size0; + else + ssize = src->layer_size; + + if (info->dst.resource->target == PIPE_TEXTURE_3D) + dsize = dslice->size0; + else + dsize = dst->layer_size; + + for (unsigned i = 0; i < info->dst.box.depth; i++) { + unsigned soff = fd_resource_offset(src, info->src.level, sbox->z + i); + unsigned doff = fd_resource_offset(dst, info->dst.level, dbox->z + i); + + debug_assert((soff + (sbox->height * spitch)) <= fd_bo_size(src->bo)); + debug_assert((doff + (dbox->height * dpitch)) <= fd_bo_size(dst->bo)); + + OUT_PKT7(ring, CP_SET_RENDER_MODE, 1); + OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(BLIT2D)); + + /* + * Emit source: + */ + OUT_PKT4(ring, REG_A5XX_RB_2D_SRC_INFO, 9); + OUT_RING(ring, A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(sfmt) | + A5XX_RB_2D_SRC_INFO_COLOR_SWAP(sswap)); + OUT_RELOC(ring, src->bo, soff, 0, 0); /* RB_2D_SRC_LO/HI */ + OUT_RING(ring, A5XX_RB_2D_SRC_SIZE_PITCH(spitch) | + A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(ssize)); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + + OUT_PKT4(ring, REG_A5XX_GRAS_2D_SRC_INFO, 1); + OUT_RING(ring, A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(sfmt) | + A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(sswap)); + + /* + * Emit destination: + */ + OUT_PKT4(ring, REG_A5XX_RB_2D_DST_INFO, 9); + OUT_RING(ring, A5XX_RB_2D_DST_INFO_COLOR_FORMAT(dfmt) | + A5XX_RB_2D_DST_INFO_COLOR_SWAP(dswap)); + OUT_RELOCW(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */ + OUT_RING(ring, A5XX_RB_2D_DST_SIZE_PITCH(dpitch) | + A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(dsize)); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + OUT_RING(ring, 0x00000000); + + OUT_PKT4(ring, REG_A5XX_GRAS_2D_DST_INFO, 1); + OUT_RING(ring, A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(dfmt) | + A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(dswap)); + + /* + * Blit command: + */ + OUT_PKT7(ring, CP_BLIT, 5); + OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_COPY)); + OUT_RING(ring, CP_BLIT_1_SRC_X1(sx1) | CP_BLIT_1_SRC_Y1(sy1)); + OUT_RING(ring, CP_BLIT_2_SRC_X2(sx2) | CP_BLIT_2_SRC_Y2(sy2)); + OUT_RING(ring, CP_BLIT_3_DST_X1(dx1) | CP_BLIT_3_DST_Y1(dy1)); + OUT_RING(ring, CP_BLIT_4_DST_X2(dx2) | CP_BLIT_4_DST_Y2(dy2)); + + OUT_PKT7(ring, CP_SET_RENDER_MODE, 1); + OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(END2D)); + } +} + +void +fd5_blitter_blit(struct fd_context *ctx, const struct pipe_blit_info *info) +{ + struct fd_batch *batch; + + if (!can_do_blit(info)) { + fd_blitter_blit(ctx, info); + return; + } + + batch = fd_batch_create(ctx, true); + + fd5_emit_restore(batch, batch->draw); + fd5_emit_lrz_flush(batch->draw); + + emit_setup(batch->draw); + + if ((info->src.resource->target == PIPE_BUFFER) && + (info->dst.resource->target == PIPE_BUFFER)) { + emit_blit_buffer(batch->draw, info); + } else { + /* I don't *think* we need to handle blits between buffer <-> !buffer */ + debug_assert(info->src.resource->target != PIPE_BUFFER); + debug_assert(info->dst.resource->target != PIPE_BUFFER); + emit_blit(batch->draw, info); + } + fd_resource(info->dst.resource)->valid = true; + batch->needs_flush = true; + + fd_batch_flush(batch, false, false); +} diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_blitter.h b/src/gallium/drivers/freedreno/a5xx/fd5_blitter.h new file mode 100644 index 00000000000..c5688a89474 --- /dev/null +++ b/src/gallium/drivers/freedreno/a5xx/fd5_blitter.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 Rob Clark <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark <[email protected]> + */ + +#ifndef FD5_BLIT_H_ +#define FD5_BLIT_H_ + +#include "pipe/p_state.h" + +#include "freedreno_context.h" + +void fd5_blitter_blit(struct fd_context *ctx, const struct pipe_blit_info *info); + +#endif /* FD5_BLIT_H_ */ diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_context.c b/src/gallium/drivers/freedreno/a5xx/fd5_context.c index 4ebbb971ad8..426a8e0b046 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_context.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_context.c @@ -27,8 +27,9 @@ #include "freedreno_query_acc.h" #include "fd5_context.h" -#include "fd5_compute.h" #include "fd5_blend.h" +#include "fd5_blitter.h" +#include "fd5_compute.h" #include "fd5_draw.h" #include "fd5_emit.h" #include "fd5_gmem.h" @@ -93,6 +94,9 @@ fd5_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags) fd5_prog_init(pctx); fd5_emit_init(pctx); + if (!(fd_mesa_debug & FD_DBG_NOBLIT)) + fd5_ctx->base.blit = fd5_blitter_blit; + pctx = fd_context_init(&fd5_ctx->base, pscreen, primtypes, priv, flags); if (!pctx) return NULL; diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_format.c b/src/gallium/drivers/freedreno/a5xx/fd5_format.c index 99dd1edc1d9..59c13fad296 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_format.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_format.c @@ -75,6 +75,9 @@ struct fd5_format { } static struct fd5_format formats[PIPE_FORMAT_COUNT] = { + /* for blitting, treat PIPE_FORMAT_NONE as 8bit R8: */ + _T(R8_UINT, 8_UINT, R8_UINT, WZYX), + /* 8-bit */ VT(R8_UNORM, 8_UNORM, R8_UNORM, WZYX), VT(R8_SNORM, 8_SNORM, R8_SNORM, WZYX), diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index f5c381e8216..0c3994730bd 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -80,6 +80,7 @@ static const struct debug_named_value debug_options[] = { {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"}, {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx+)"}, {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"}, + {"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"}, DEBUG_NAMED_VALUE_END }; diff --git a/src/gallium/drivers/freedreno/freedreno_util.h b/src/gallium/drivers/freedreno/freedreno_util.h index b6f4771390e..f8bde6a88c2 100644 --- a/src/gallium/drivers/freedreno/freedreno_util.h +++ b/src/gallium/drivers/freedreno/freedreno_util.h @@ -81,6 +81,7 @@ enum adreno_stencil_op fd_stencil_op(unsigned op); #define FD_DBG_NOGROW 0x10000 #define FD_DBG_LRZ 0x20000 #define FD_DBG_NOINDR 0x40000 +#define FD_DBG_NOBLIT 0x80000 extern int fd_mesa_debug; extern bool fd_binning_enabled; diff --git a/src/gallium/drivers/freedreno/meson.build b/src/gallium/drivers/freedreno/meson.build index 7c45d4fe844..bc64d3090f4 100644 --- a/src/gallium/drivers/freedreno/meson.build +++ b/src/gallium/drivers/freedreno/meson.build @@ -150,6 +150,8 @@ files_libfreedreno = files( 'a5xx/a5xx.xml.h', 'a5xx/fd5_blend.c', 'a5xx/fd5_blend.h', + 'a5xx/fd5_blitter.c', + 'a5xx/fd5_blitter.h', 'a5xx/fd5_compute.c', 'a5xx/fd5_compute.h', 'a5xx/fd5_context.c', |