diff options
| -rw-r--r-- | src/gallium/drivers/r600/r600_blit.c | 5 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/r600_texture.c | 9 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_blit.c | 2 |
3 files changed, 10 insertions, 6 deletions
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index 962be60c108..c98206fe903 100644 --- a/src/gallium/drivers/r600/r600_blit.c +++ b/src/gallium/drivers/r600/r600_blit.c @@ -429,7 +429,8 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers, * disable fast clear for texture array. */ /* Only use htile for first level */ - if (rtex->htile_buffer && !level && rtex->surface.array_size == 1) { + if (rtex->htile_buffer && !level && + util_max_layer(&rtex->resource.b.b, level) == 0) { if (rtex->depth_clear_value != depth) { rtex->depth_clear_value = depth; rctx->db_state.atom.dirty = true; @@ -828,7 +829,7 @@ static void r600_flush_resource(struct pipe_context *ctx, if (!rtex->is_depth && rtex->cmask.size) { r600_blit_decompress_color(ctx, rtex, 0, res->last_level, - 0, res->array_size - 1); + 0, util_max_layer(res, 0)); } } diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index ac9f6808b3e..482bbff4e63 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -380,7 +380,8 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen, out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1; out->alignment = MAX2(256, base_align); - out->size = rtex->surface.array_size * align(slice_bytes, base_align); + out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) * + align(slice_bytes, base_align); } static void si_texture_get_cmask_info(struct r600_common_screen *rscreen, @@ -427,7 +428,8 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen, out->slice_tile_max -= 1; out->alignment = MAX2(256, base_align); - out->size = rtex->surface.array_size * align(slice_bytes, base_align); + out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) * + align(slice_bytes, base_align); } static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen, @@ -523,7 +525,8 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen, pipe_interleave_bytes = rscreen->tiling_info.group_bytes; base_align = num_pipes * pipe_interleave_bytes; - return rtex->surface.array_size * align(slice_bytes, base_align); + return (util_max_layer(&rtex->resource.b.b, 0) + 1) * + align(slice_bytes, base_align); } static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen, diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index 9b0186761a4..bc31dfd55a8 100644 --- a/src/gallium/drivers/radeonsi/si_blit.c +++ b/src/gallium/drivers/radeonsi/si_blit.c @@ -753,7 +753,7 @@ static void si_flush_resource(struct pipe_context *ctx, if (!rtex->is_depth && rtex->cmask.size) { si_blit_decompress_color(ctx, rtex, 0, res->last_level, - 0, res->array_size - 1); + 0, util_max_layer(res, 0)); } } |