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-rw-r--r--src/intel/blorp/blorp.c2
-rw-r--r--src/intel/blorp/blorp.h19
-rw-r--r--src/intel/blorp/blorp_clear.c2
-rw-r--r--src/intel/blorp/blorp_genX_exec.h39
-rw-r--r--src/intel/blorp/blorp_priv.h2
-rw-r--r--src/intel/vulkan/anv_blorp.c15
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.c16
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_clear.c4
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c14
10 files changed, 44 insertions, 71 deletions
diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index 52675ec4ac5..e348cafb2e5 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -295,7 +295,7 @@ blorp_ensure_sf_program(struct blorp_context *blorp,
void
blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
uint32_t level, uint32_t start_layer, uint32_t num_layers,
- enum blorp_hiz_op op)
+ enum isl_aux_op op)
{
struct blorp_params params;
blorp_params_init(&params);
diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index f1be12ba91e..ce3762c42fa 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -207,27 +207,10 @@ blorp_mcs_partial_resolve(struct blorp_batch *batch,
enum isl_format format,
uint32_t start_layer, uint32_t num_layers);
-/**
- * For an overview of the HiZ operations, see the following sections of the
- * Sandy Bridge PRM, Volume 1, Part2:
- * - 7.5.3.1 Depth Buffer Clear
- * - 7.5.3.2 Depth Buffer Resolve
- * - 7.5.3.3 Hierarchical Depth Buffer Resolve
- *
- * Of these, two get entered in the resolve map as needing to be done to the
- * buffer: depth resolve and hiz resolve.
- */
-enum blorp_hiz_op {
- BLORP_HIZ_OP_NONE,
- BLORP_HIZ_OP_DEPTH_CLEAR,
- BLORP_HIZ_OP_DEPTH_RESOLVE,
- BLORP_HIZ_OP_HIZ_RESOLVE,
-};
-
void
blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
uint32_t level, uint32_t start_layer, uint32_t num_layers,
- enum blorp_hiz_op op);
+ enum isl_aux_op op);
#ifdef __cplusplus
} /* end extern "C" */
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index d205e5becae..421a6c5d345 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -630,7 +630,7 @@ blorp_gen8_hiz_clear_attachments(struct blorp_batch *batch,
struct blorp_params params;
blorp_params_init(&params);
params.num_layers = 1;
- params.hiz_op = BLORP_HIZ_OP_DEPTH_CLEAR;
+ params.hiz_op = ISL_AUX_OP_FAST_CLEAR;
params.x0 = x0;
params.y0 = y0;
params.x1 = x1;
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 8d007b818ad..5e1312aa305 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -787,16 +787,16 @@ blorp_emit_ps_config(struct blorp_batch *batch,
blorp_emit(batch, GENX(3DSTATE_WM), wm) {
switch (params->hiz_op) {
- case BLORP_HIZ_OP_DEPTH_CLEAR:
+ case ISL_AUX_OP_FAST_CLEAR:
wm.DepthBufferClear = true;
break;
- case BLORP_HIZ_OP_DEPTH_RESOLVE:
+ case ISL_AUX_OP_FULL_RESOLVE:
wm.DepthBufferResolveEnable = true;
break;
- case BLORP_HIZ_OP_HIZ_RESOLVE:
+ case ISL_AUX_OP_AMBIGUATE:
wm.HierarchicalDepthBufferResolveEnable = true;
break;
- case BLORP_HIZ_OP_NONE:
+ case ISL_AUX_OP_NONE:
break;
default:
unreachable("not reached");
@@ -872,16 +872,16 @@ blorp_emit_ps_config(struct blorp_batch *batch,
batch->blorp->isl_dev->info->max_wm_threads - 1;
switch (params->hiz_op) {
- case BLORP_HIZ_OP_DEPTH_CLEAR:
+ case ISL_AUX_OP_FAST_CLEAR:
wm.DepthBufferClear = true;
break;
- case BLORP_HIZ_OP_DEPTH_RESOLVE:
+ case ISL_AUX_OP_FULL_RESOLVE:
wm.DepthBufferResolveEnable = true;
break;
- case BLORP_HIZ_OP_HIZ_RESOLVE:
+ case ISL_AUX_OP_AMBIGUATE:
wm.HierarchicalDepthBufferResolveEnable = true;
break;
- case BLORP_HIZ_OP_NONE:
+ case ISL_AUX_OP_NONE:
break;
default:
unreachable("not reached");
@@ -1014,7 +1014,7 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch,
ds.DepthBufferWriteEnable = true;
switch (params->hiz_op) {
- case BLORP_HIZ_OP_NONE:
+ case ISL_AUX_OP_NONE:
ds.DepthTestEnable = true;
ds.DepthTestFunction = COMPAREFUNCTION_ALWAYS;
break;
@@ -1024,15 +1024,17 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch,
* - 7.5.3.2 Depth Buffer Resolve
* - 7.5.3.3 Hierarchical Depth Buffer Resolve
*/
- case BLORP_HIZ_OP_DEPTH_RESOLVE:
+ case ISL_AUX_OP_FULL_RESOLVE:
ds.DepthTestEnable = true;
ds.DepthTestFunction = COMPAREFUNCTION_NEVER;
break;
- case BLORP_HIZ_OP_DEPTH_CLEAR:
- case BLORP_HIZ_OP_HIZ_RESOLVE:
+ case ISL_AUX_OP_FAST_CLEAR:
+ case ISL_AUX_OP_AMBIGUATE:
ds.DepthTestEnable = false;
break;
+ case ISL_AUX_OP_PARTIAL_RESOLVE:
+ unreachable("Invalid HIZ op");
}
}
@@ -1522,7 +1524,7 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
* requested.
*/
if (params->stencil.enabled)
- assert(params->hiz_op == BLORP_HIZ_OP_DEPTH_CLEAR);
+ assert(params->hiz_op == ISL_AUX_OP_FAST_CLEAR);
/* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP:
*
@@ -1547,21 +1549,22 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
blorp_emit(batch, GENX(3DSTATE_WM_HZ_OP), hzp) {
switch (params->hiz_op) {
- case BLORP_HIZ_OP_DEPTH_CLEAR:
+ case ISL_AUX_OP_FAST_CLEAR:
hzp.StencilBufferClearEnable = params->stencil.enabled;
hzp.DepthBufferClearEnable = params->depth.enabled;
hzp.StencilClearValue = params->stencil_ref;
hzp.FullSurfaceDepthandStencilClear = params->full_surface_hiz_op;
break;
- case BLORP_HIZ_OP_DEPTH_RESOLVE:
+ case ISL_AUX_OP_FULL_RESOLVE:
assert(params->full_surface_hiz_op);
hzp.DepthBufferResolveEnable = true;
break;
- case BLORP_HIZ_OP_HIZ_RESOLVE:
+ case ISL_AUX_OP_AMBIGUATE:
assert(params->full_surface_hiz_op);
hzp.HierarchicalDepthBufferResolveEnable = true;
break;
- case BLORP_HIZ_OP_NONE:
+ case ISL_AUX_OP_PARTIAL_RESOLVE:
+ case ISL_AUX_OP_NONE:
unreachable("Invalid HIZ op");
}
@@ -1605,7 +1608,7 @@ static void
blorp_exec(struct blorp_batch *batch, const struct blorp_params *params)
{
#if GEN_GEN >= 8
- if (params->hiz_op != BLORP_HIZ_OP_NONE) {
+ if (params->hiz_op != ISL_AUX_OP_NONE) {
blorp_emit_gen8_hiz_op(batch, params);
return;
}
diff --git a/src/intel/blorp/blorp_priv.h b/src/intel/blorp/blorp_priv.h
index ef3fc6d378e..3fd2203959f 100644
--- a/src/intel/blorp/blorp_priv.h
+++ b/src/intel/blorp/blorp_priv.h
@@ -190,7 +190,7 @@ struct blorp_params
uint32_t depth_format;
struct brw_blorp_surface_info src;
struct brw_blorp_surface_info dst;
- enum blorp_hiz_op hiz_op;
+ enum isl_aux_op hiz_op;
bool full_surface_hiz_op;
enum isl_aux_op fast_clear_op;
bool color_write_disable[4];
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 7d0ded3423c..d38b343671f 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1618,18 +1618,6 @@ anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
blorp_batch_finish(&batch);
}
-static enum blorp_hiz_op
-isl_to_blorp_hiz_op(enum isl_aux_op isl_op)
-{
- switch (isl_op) {
- case ISL_AUX_OP_FAST_CLEAR: return BLORP_HIZ_OP_DEPTH_CLEAR;
- case ISL_AUX_OP_FULL_RESOLVE: return BLORP_HIZ_OP_DEPTH_RESOLVE;
- case ISL_AUX_OP_AMBIGUATE: return BLORP_HIZ_OP_HIZ_RESOLVE;
- default:
- unreachable("Unsupported HiZ aux op");
- }
-}
-
void
anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
@@ -1651,8 +1639,7 @@ anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
ISL_AUX_USAGE_HIZ, &surf);
surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
- blorp_hiz_op(&batch, &surf, level, base_layer, layer_count,
- isl_to_blorp_hiz_op(hiz_op));
+ blorp_hiz_op(&batch, &surf, level, base_layer, layer_count, hiz_op);
blorp_batch_finish(&batch);
}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 70180630124..aa62abde9c4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1525,26 +1525,26 @@ brw_blorp_mcs_partial_resolve(struct brw_context *brw,
void
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
unsigned int level, unsigned int start_layer,
- unsigned int num_layers, enum blorp_hiz_op op)
+ unsigned int num_layers, enum isl_aux_op op)
{
assert(intel_miptree_level_has_hiz(mt, level));
- assert(op != BLORP_HIZ_OP_NONE);
+ assert(op != ISL_AUX_OP_NONE);
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const char *opname = NULL;
switch (op) {
- case BLORP_HIZ_OP_DEPTH_RESOLVE:
+ case ISL_AUX_OP_FULL_RESOLVE:
opname = "depth resolve";
break;
- case BLORP_HIZ_OP_HIZ_RESOLVE:
+ case ISL_AUX_OP_AMBIGUATE:
opname = "hiz ambiguate";
break;
- case BLORP_HIZ_OP_DEPTH_CLEAR:
+ case ISL_AUX_OP_FAST_CLEAR:
opname = "depth clear";
break;
- case BLORP_HIZ_OP_NONE:
- opname = "noop?";
- break;
+ case ISL_AUX_OP_PARTIAL_RESOLVE:
+ case ISL_AUX_OP_NONE:
+ unreachable("Invalid HiZ op");
}
DBG("%s %s to mt %p level %d layers %d-%d\n",
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index d255fe17184..a2eeb3994ad 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -109,7 +109,7 @@ brw_blorp_mcs_partial_resolve(struct brw_context *brw,
void
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
unsigned int level, unsigned int start_layer,
- unsigned int num_layers, enum blorp_hiz_op op);
+ unsigned int num_layers, enum isl_aux_op op);
void gen4_blorp_exec(struct blorp_batch *batch,
const struct blorp_params *params);
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index fe8634b3b34..8aa83722ee9 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -206,7 +206,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
* value so this shouldn't happen often.
*/
intel_hiz_exec(brw, mt, level, layer, 1,
- BLORP_HIZ_OP_DEPTH_RESOLVE);
+ ISL_AUX_OP_FULL_RESOLVE);
intel_miptree_set_aux_state(brw, mt, level, layer, 1,
ISL_AUX_STATE_RESOLVED);
}
@@ -243,7 +243,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
if (aux_state != ISL_AUX_STATE_CLEAR) {
intel_hiz_exec(brw, mt, depth_irb->mt_level,
depth_irb->mt_layer + a, 1,
- BLORP_HIZ_OP_DEPTH_CLEAR);
+ ISL_AUX_OP_FAST_CLEAR);
}
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a388fb38b1f..22977d6659e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2308,17 +2308,17 @@ intel_miptree_prepare_hiz_access(struct brw_context *brw,
{
assert(aux_usage == ISL_AUX_USAGE_NONE || aux_usage == ISL_AUX_USAGE_HIZ);
- enum blorp_hiz_op hiz_op = BLORP_HIZ_OP_NONE;
+ enum isl_aux_op hiz_op = ISL_AUX_OP_NONE;
switch (intel_miptree_get_aux_state(mt, level, layer)) {
case ISL_AUX_STATE_CLEAR:
case ISL_AUX_STATE_COMPRESSED_CLEAR:
if (aux_usage != ISL_AUX_USAGE_HIZ || !fast_clear_supported)
- hiz_op = BLORP_HIZ_OP_DEPTH_RESOLVE;
+ hiz_op = ISL_AUX_OP_FULL_RESOLVE;
break;
case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
if (aux_usage != ISL_AUX_USAGE_HIZ)
- hiz_op = BLORP_HIZ_OP_DEPTH_RESOLVE;
+ hiz_op = ISL_AUX_OP_FULL_RESOLVE;
break;
case ISL_AUX_STATE_PASS_THROUGH:
@@ -2327,23 +2327,23 @@ intel_miptree_prepare_hiz_access(struct brw_context *brw,
case ISL_AUX_STATE_AUX_INVALID:
if (aux_usage == ISL_AUX_USAGE_HIZ)
- hiz_op = BLORP_HIZ_OP_HIZ_RESOLVE;
+ hiz_op = ISL_AUX_OP_AMBIGUATE;
break;
case ISL_AUX_STATE_PARTIAL_CLEAR:
unreachable("Invalid HiZ state");
}
- if (hiz_op != BLORP_HIZ_OP_NONE) {
+ if (hiz_op != ISL_AUX_OP_NONE) {
intel_hiz_exec(brw, mt, level, layer, 1, hiz_op);
switch (hiz_op) {
- case BLORP_HIZ_OP_DEPTH_RESOLVE:
+ case ISL_AUX_OP_FULL_RESOLVE:
intel_miptree_set_aux_state(brw, mt, level, layer, 1,
ISL_AUX_STATE_RESOLVED);
break;
- case BLORP_HIZ_OP_HIZ_RESOLVE:
+ case ISL_AUX_OP_AMBIGUATE:
/* The HiZ resolve operation is actually an ambiguate */
intel_miptree_set_aux_state(brw, mt, level, layer, 1,
ISL_AUX_STATE_PASS_THROUGH);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-03 00:12:57 +0000