diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/Makefile.sources | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_tex_layout.c | 105 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_tex_layout.c | 147 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_tex_layout.h | 38 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_tex_validate.c | 1 |
6 files changed, 102 insertions, 191 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources index e876c180e1e..1f401fe78c3 100644 --- a/src/mesa/drivers/dri/i965/Makefile.sources +++ b/src/mesa/drivers/dri/i965/Makefile.sources @@ -24,7 +24,6 @@ i965_FILES = \ intel_tex.c \ intel_tex_copy.c \ intel_tex_image.c \ - intel_tex_layout.c \ intel_tex_subimage.c \ intel_tex_validate.c \ brw_blorp.cpp \ diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index f4029c431ab..0a46d1c4032 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -33,12 +33,111 @@ */ #include "intel_mipmap_tree.h" -#include "intel_tex_layout.h" #include "intel_context.h" #include "main/macros.h" #define FILE_DEBUG_FLAG DEBUG_MIPTREE +static unsigned int +intel_horizontal_texture_alignment_unit(struct intel_context *intel, + gl_format format) +{ + /** + * From the "Alignment Unit Size" section of various specs, namely: + * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4 + * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4. + * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4 + * - BSpec (for Ivybridge and slight variations in separate stencil) + * + * +----------------------------------------------------------------------+ + * | | alignment unit width ("i") | + * | Surface Property |-----------------------------| + * | | 915 | 965 | ILK | SNB | IVB | + * +----------------------------------------------------------------------+ + * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 | + * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 | + * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 | + * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 | + * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 | + * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 | + * | All Others | 4 | 4 | 4 | 4 | 4 | + * +----------------------------------------------------------------------+ + * + * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE + * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8. + */ + if (_mesa_is_format_compressed(format)) { + /* The hardware alignment requirements for compressed textures + * happen to match the block boundaries. + */ + unsigned int i, j; + _mesa_get_format_block_size(format, &i, &j); + return i; + } + + if (format == MESA_FORMAT_S8) + return 8; + + /* The depth alignment requirements in the table above are for rendering to + * depth miplevels using the LOD control fields. We don't use LOD control + * fields, and instead use page offsets plus intra-tile x/y offsets, which + * require that the low 3 bits are zero. To reduce the number of x/y + * offset workaround blits we do, align the X to 8, which depth texturing + * can handle (sadly, it can't handle 8 in the Y direction). + */ + if (intel->gen >= 7 && + _mesa_get_format_base_format(format) == GL_DEPTH_COMPONENT) + return 8; + + return 4; +} + +static unsigned int +intel_vertical_texture_alignment_unit(struct intel_context *intel, + gl_format format) +{ + /** + * From the "Alignment Unit Size" section of various specs, namely: + * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4 + * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4. + * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4 + * - BSpec (for Ivybridge and slight variations in separate stencil) + * + * +----------------------------------------------------------------------+ + * | | alignment unit height ("j") | + * | Surface Property |-----------------------------| + * | | 915 | 965 | ILK | SNB | IVB | + * +----------------------------------------------------------------------+ + * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 | + * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 | + * | Depth Buffer | 2 | 2 | 2 | 4 | 4 | + * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 | + * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 | + * | All Others | 2 | 2 | 2 | 2 | 2 | + * +----------------------------------------------------------------------+ + * + * On SNB+, non-special cases can be overridden by setting the SURFACE_STATE + * "Surface Vertical Alignment" field to VALIGN_2 or VALIGN_4. + * + * We currently don't support multisampling. + */ + if (_mesa_is_format_compressed(format)) + return 4; + + if (format == MESA_FORMAT_S8) + return intel->gen >= 7 ? 8 : 4; + + GLenum base_format = _mesa_get_format_base_format(format); + + if (intel->gen >= 6 && + (base_format == GL_DEPTH_COMPONENT || + base_format == GL_DEPTH_STENCIL)) { + return 4; + } + + return 2; +} + static void brw_miptree_layout_2d(struct intel_mipmap_tree *mt) { @@ -212,8 +311,8 @@ brw_miptree_layout_texture_3d(struct intel_context *intel, void brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt) { - intel_get_texture_alignment_unit(intel, mt->format, - &mt->align_w, &mt->align_h); + mt->align_w = intel_horizontal_texture_alignment_unit(intel, mt->format); + mt->align_h = intel_vertical_texture_alignment_unit(intel, mt->format); switch (mt->target) { case GL_TEXTURE_CUBE_MAP: diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index bebfe511bb4..af869905a96 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -34,7 +34,6 @@ #include "intel_mipmap_tree.h" #include "intel_regions.h" #include "intel_resolve_map.h" -#include "intel_tex_layout.h" #include "intel_tex.h" #include "intel_blit.h" diff --git a/src/mesa/drivers/dri/i965/intel_tex_layout.c b/src/mesa/drivers/dri/i965/intel_tex_layout.c deleted file mode 100644 index 60f3f82f09d..00000000000 --- a/src/mesa/drivers/dri/i965/intel_tex_layout.c +++ /dev/null @@ -1,147 +0,0 @@ -/************************************************************************** - * - * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - /* - * Authors: - * Keith Whitwell <[email protected]> - * Michel Dänzer <[email protected]> - */ - -#include "intel_mipmap_tree.h" -#include "intel_tex_layout.h" -#include "intel_context.h" - -#include "main/image.h" -#include "main/macros.h" - -static unsigned int -intel_horizontal_texture_alignment_unit(struct intel_context *intel, - gl_format format) -{ - /** - * From the "Alignment Unit Size" section of various specs, namely: - * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4 - * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4. - * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4 - * - BSpec (for Ivybridge and slight variations in separate stencil) - * - * +----------------------------------------------------------------------+ - * | | alignment unit width ("i") | - * | Surface Property |-----------------------------| - * | | 915 | 965 | ILK | SNB | IVB | - * +----------------------------------------------------------------------+ - * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 | - * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 | - * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 | - * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 | - * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 | - * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 | - * | All Others | 4 | 4 | 4 | 4 | 4 | - * +----------------------------------------------------------------------+ - * - * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE - * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8. - */ - if (_mesa_is_format_compressed(format)) { - /* The hardware alignment requirements for compressed textures - * happen to match the block boundaries. - */ - unsigned int i, j; - _mesa_get_format_block_size(format, &i, &j); - return i; - } - - if (format == MESA_FORMAT_S8) - return 8; - - /* The depth alignment requirements in the table above are for rendering to - * depth miplevels using the LOD control fields. We don't use LOD control - * fields, and instead use page offsets plus intra-tile x/y offsets, which - * require that the low 3 bits are zero. To reduce the number of x/y - * offset workaround blits we do, align the X to 8, which depth texturing - * can handle (sadly, it can't handle 8 in the Y direction). - */ - if (intel->gen >= 7 && - _mesa_get_format_base_format(format) == GL_DEPTH_COMPONENT) - return 8; - - return 4; -} - -static unsigned int -intel_vertical_texture_alignment_unit(struct intel_context *intel, - gl_format format) -{ - /** - * From the "Alignment Unit Size" section of various specs, namely: - * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4 - * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4. - * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4 - * - BSpec (for Ivybridge and slight variations in separate stencil) - * - * +----------------------------------------------------------------------+ - * | | alignment unit height ("j") | - * | Surface Property |-----------------------------| - * | | 915 | 965 | ILK | SNB | IVB | - * +----------------------------------------------------------------------+ - * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 | - * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 | - * | Depth Buffer | 2 | 2 | 2 | 4 | 4 | - * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 | - * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 | - * | All Others | 2 | 2 | 2 | 2 | 2 | - * +----------------------------------------------------------------------+ - * - * On SNB+, non-special cases can be overridden by setting the SURFACE_STATE - * "Surface Vertical Alignment" field to VALIGN_2 or VALIGN_4. - * - * We currently don't support multisampling. - */ - if (_mesa_is_format_compressed(format)) - return 4; - - if (format == MESA_FORMAT_S8) - return intel->gen >= 7 ? 8 : 4; - - GLenum base_format = _mesa_get_format_base_format(format); - - if (intel->gen >= 6 && - (base_format == GL_DEPTH_COMPONENT || - base_format == GL_DEPTH_STENCIL)) { - return 4; - } - - return 2; -} - -void -intel_get_texture_alignment_unit(struct intel_context *intel, - gl_format format, - unsigned int *w, unsigned int *h) -{ - *w = intel_horizontal_texture_alignment_unit(intel, format); - *h = intel_vertical_texture_alignment_unit(intel, format); -} diff --git a/src/mesa/drivers/dri/i965/intel_tex_layout.h b/src/mesa/drivers/dri/i965/intel_tex_layout.h deleted file mode 100644 index f769583df89..00000000000 --- a/src/mesa/drivers/dri/i965/intel_tex_layout.h +++ /dev/null @@ -1,38 +0,0 @@ -/************************************************************************** - * - * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - /* - * Authors: - * Keith Whitwell <[email protected]> - * Michel Dänzer <[email protected]> - */ - -#include "main/macros.h" - -void -intel_get_texture_alignment_unit(struct intel_context *intel, - gl_format format, - unsigned int *w, unsigned int *h); diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c index a8a8647eb3c..049d2472da0 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c @@ -7,7 +7,6 @@ #include "intel_mipmap_tree.h" #include "intel_blit.h" #include "intel_tex.h" -#include "intel_tex_layout.h" #define FILE_DEBUG_FLAG DEBUG_TEXTURE |