diff options
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 4 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 5 | ||||
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 12 |
3 files changed, 16 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 4fd0f4c00d1..312694cb37d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1557,7 +1557,9 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer, ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count); if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) { - if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) + radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param); + else if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param); else radeon_set_context_reg(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index ffedf237769..1f5fe50f62e 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2149,10 +2149,15 @@ radv_pipeline_init(struct radv_pipeline *pipeline, S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); else stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS); + } else if (radv_pipeline_has_gs(pipeline)) stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) | S_028B54_GS_EN(1) | S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); + + if (device->physical_device->rad_info.chip_class >= GFX9) + stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2); + pipeline->graphics.vgt_shader_stages_en = stages; if (radv_pipeline_has_gs(pipeline)) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 397ea810084..a10034e4f20 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -716,7 +716,8 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */ if (cmd_buffer->device->has_distributed_tess) { if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) { - partial_es_wave = true; + if (chip_class <= VI) + partial_es_wave = true; if (family == CHIP_TONGA || family == CHIP_FIJI || @@ -784,7 +785,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, assert(wd_switch_on_eop || !ia_switch_on_eop); } /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */ - if (ia_switch_on_eoi) + if (chip_class <= VI && ia_switch_on_eoi) partial_es_wave = true; if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) { @@ -806,8 +807,11 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) | S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) | S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0) | - S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class >= VI ? - max_primgroup_in_wave : 0); + /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */ + S_028AA8_MAX_PRIMGRP_IN_WAVE(chip_class == VI ? + max_primgroup_in_wave : 0) | + S_030960_EN_INST_OPT_BASIC(chip_class >= GFX9) | + S_030960_EN_INST_OPT_ADV(chip_class >= GFX9); } |