diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 18 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_shader.cpp | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 1 |
5 files changed, 9 insertions, 14 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 0542b43a5cb..f66ba473411 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1549,20 +1549,6 @@ fs_visitor::emit_gs_thread_end() void fs_visitor::assign_curb_setup() { - if (dispatch_width == 8) { - prog_data->dispatch_grf_start_reg = payload.num_regs; - } else { - if (stage == MESA_SHADER_FRAGMENT) { - brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; - prog_data->dispatch_grf_start_reg_16 = payload.num_regs; - } else if (stage == MESA_SHADER_COMPUTE) { - brw_cs_prog_data *prog_data = (brw_cs_prog_data*) this->prog_data; - prog_data->dispatch_grf_start_reg_16 = payload.num_regs; - } else { - unreachable("Unsupported shader type!"); - } - } - prog_data->curb_read_length = ALIGN(stage_prog_data->nr_params, 8) / 8; /* Map the offsets in the UNIFORM file to fixed HW regs. */ @@ -6029,6 +6015,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data, return NULL; } else if (likely(!(INTEL_DEBUG & DEBUG_NO8))) { simd8_cfg = v8.cfg; + prog_data->base.dispatch_grf_start_reg = v8.payload.num_regs; } if (!v8.simd16_unsupported && @@ -6044,6 +6031,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data, v16.fail_msg); } else { simd16_cfg = v16.cfg; + prog_data->dispatch_grf_start_reg_16 = v16.payload.num_regs; } } @@ -6167,6 +6155,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, } else { cfg = v8.cfg; prog_data->simd_size = 8; + prog_data->base.dispatch_grf_start_reg = v8.payload.num_regs; } } @@ -6191,6 +6180,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, } else { cfg = v16.cfg; prog_data->simd_size = 16; + prog_data->dispatch_grf_start_reg_16 = v16.payload.num_regs; } } diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index d80618f6e6c..48828df4c8e 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -1387,6 +1387,7 @@ brw_compile_tes(const struct brw_compiler *compiler, return NULL; } + prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8; fs_generator g(compiler, log_data, mem_ctx, (void *) key, diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 815eaed6859..385afc1ee46 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -2140,6 +2140,8 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, return NULL; } + prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; + fs_generator g(compiler, log_data, mem_ctx, (void *) key, &prog_data->base.base, v.promoted_constants, v.runtime_check_aads_emit, MESA_SHADER_VERTEX); diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp index b3b13a16c95..f591addfc04 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp @@ -815,6 +815,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, shader_time_index); if (v.run_gs()) { prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8; + prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; fs_generator g(compiler, log_data, mem_ctx, &c.key, &prog_data->base.base, v.promoted_constants, diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp index 6d39474e251..2e1a9a671af 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp @@ -507,6 +507,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, return NULL; } + prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8; fs_generator g(compiler, log_data, mem_ctx, (void *) key, |