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-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c2
-rw-r--r--src/mesa/drivers/dri/r600/r700_render.c6
-rw-r--r--src/mesa/drivers/dri/r600/r700_state.c80
-rw-r--r--src/mesa/drivers/dri/r600/r700_state.h4
4 files changed, 40 insertions, 52 deletions
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 78779e841d7..e5e0f556cbe 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -322,7 +322,7 @@ void r700SetupVTXConstants(GLcontext * ctx,
unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
if (!paos->bo)
- return GL_FALSE;
+ return;
if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index 20376d2c36d..6705dbcf4b9 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -289,7 +289,6 @@ void r700EmitState(GLcontext * ctx)
rcommonEnsureCmdBufSpace(&context->radeon,
context->radeon.hw.max_state_size, __FUNCTION__);
- r700Start3D(context);
r700SendSQConfig(context);
r700SendUCPState(context);
@@ -308,13 +307,12 @@ static GLboolean r700RunRender(GLcontext * ctx,
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *vb = &tnl->vb;
+ r700Start3D(context);
+
r700UpdateShaders(ctx);
r700SetScissor(context);
r700SetupShaders(ctx);
- r700SetRenderTarget(context, 0);
- r700SetDepthTarget(context);
-
r700EmitState(ctx);
/* richard test code */
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 7f54cf9f565..835b5e18c2c 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -60,6 +60,8 @@ static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
static void r700UpdatePolygonMode(GLcontext * ctx);
static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
static void r700SetStencilState(GLcontext * ctx, GLboolean state);
+static void r700SetRenderTarget(context_t *context, int id);
+static void r700SetDepthTarget(context_t *context);
void r700SetDefaultStates(context_t *context) //--------------------
{
@@ -158,21 +160,10 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------
*/
void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
{
-#if 0 /* to be enabled */
- context_t *context = R700_CONTEXT(ctx);
+ context_t *context = R700_CONTEXT(ctx);
- switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
- {
- case BUFFER_FRONT_LEFT:
- context->target.rt = context->screen->frontBuffer;
- break;
- case BUFFER_BACK_LEFT:
- context->target.rt = context->screen->backBuffer;
- break;
- default:
- memset (&context->target.rt, sizeof(context->target.rt), 0);
- }
-#endif /* to be enabled */
+ r700SetRenderTarget(context, 0);
+ r700SetDepthTarget(context);
}
static void r700FetchStateParameter(GLcontext * ctx,
@@ -1357,22 +1348,22 @@ void r700SetScissor(context_t *context) //---------------
r700->viewport[id].enabled = GL_TRUE;
}
-void r700SetRenderTarget(context_t *context, int id)
+static void r700SetRenderTarget(context_t *context, int id)
{
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
struct radeon_renderbuffer *rrb;
unsigned int nPitchInPixel;
+ rrb = radeon_get_colorbuffer(&context->radeon);
+ if (!rrb || !rrb->bo) {
+ fprintf(stderr, "no rrb\n");
+ return;
+ }
+
/* screen/window/view */
SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
- rrb = radeon_get_colorbuffer(&context->radeon);
- if (!rrb || !rrb->bo) {
- fprintf(stderr, "no rrb\n");
- return;
- }
-
/* color buffer */
r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
@@ -1405,39 +1396,22 @@ void r700SetRenderTarget(context_t *context, int id)
r700->render_target[id].enabled = GL_TRUE;
}
-void r700SetDepthTarget(context_t *context)
+static void r700SetDepthTarget(context_t *context)
{
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
struct radeon_renderbuffer *rrb;
unsigned int nPitchInPixel;
+ rrb = radeon_get_depthbuffer(&context->radeon);
+ if (!rrb)
+ return;
+
/* depth buf */
r700->DB_DEPTH_SIZE.u32All = 0;
r700->DB_DEPTH_BASE.u32All = 0;
r700->DB_DEPTH_INFO.u32All = 0;
-
- r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
- r700->DB_DEPTH_VIEW.u32All = 0;
- r700->DB_RENDER_CONTROL.u32All = 0;
- SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
- SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
- r700->DB_RENDER_OVERRIDE.u32All = 0;
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
- SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
-
- r700->DB_ALPHA_TO_MASK.u32All = 0;
- SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
- SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
- SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
- SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
-
- rrb = radeon_get_depthbuffer(&context->radeon);
- if (!rrb)
- return;
+ r700->DB_DEPTH_VIEW.u32All = 0;
nPitchInPixel = rrb->pitch/rrb->cpp;
@@ -1787,6 +1761,24 @@ void r700InitState(GLcontext * ctx) //-------------------
r700DepthFunc(ctx, ctx->Depth.Func);
SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
+ r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
+
+ r700->DB_RENDER_CONTROL.u32All = 0;
+ SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
+ SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
+ r700->DB_RENDER_OVERRIDE.u32All = 0;
+ if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
+ SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
+ SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
+ SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
+ SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
+
+ r700->DB_ALPHA_TO_MASK.u32All = 0;
+ SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
+ SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
+ SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
+ SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
+
/* stencil */
r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h
index 23246367db8..30eb54e8b0a 100644
--- a/src/mesa/drivers/dri/r600/r700_state.h
+++ b/src/mesa/drivers/dri/r600/r700_state.h
@@ -42,10 +42,8 @@ extern void r700UpdateDrawBuffer (GLcontext * ctx);
extern void r700InitState (GLcontext * ctx);
extern void r700InitStateFuncs (struct dd_function_table *functions);
-extern void r700SetRenderTarget(context_t *context, int id);
extern void r700SetDefaultStates(context_t * context);
-void r700SetScissor(context_t *context);
-void r700SetDepthTarget(context_t *context);
+extern void r700SetScissor(context_t *context);
#endif /* _R600_SCREEN_H */
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-01 22:38:37 +0000