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-rw-r--r--src/mesa/drivers/dri/i965/brw_context.c8
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h5
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c10
3 files changed, 8 insertions, 15 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 28118b967c5..cad83e24c88 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -718,14 +718,6 @@ brwCreateContext(gl_api api,
brw_init_surface_formats(brw);
- if (brw->is_g4x || brw->gen >= 5) {
- brw->CMD_VF_STATISTICS = GM45_3DSTATE_VF_STATISTICS;
- brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
- } else {
- brw->CMD_VF_STATISTICS = GEN4_3DSTATE_VF_STATISTICS;
- brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965;
- }
-
brw->max_vs_threads = devinfo->max_vs_threads;
brw->max_gs_threads = devinfo->max_gs_threads;
brw->max_wm_threads = devinfo->max_wm_threads;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 1f7108f30e9..f30d42c552e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1172,11 +1172,6 @@ struct brw_context
*/
int num_samples;
- /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
- uint32_t CMD_VF_STATISTICS;
- /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
- uint32_t CMD_PIPELINE_SELECT;
-
/**
* Platform specific constants containing the maximum number of threads
* for each pipeline stage.
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index c8fb6f312d1..a6b108b6983 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -896,13 +896,17 @@ const struct brw_tracked_state brw_line_stipple = {
void
brw_upload_invariant_state(struct brw_context *brw)
{
+ const bool is_965 = brw->gen == 4 && !brw->is_g4x;
+
/* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
if (brw->gen == 6)
intel_emit_post_sync_nonzero_flush(brw);
/* Select the 3D pipeline (as opposed to media) */
+ const uint32_t _3DSTATE_PIPELINE_SELECT =
+ is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
BEGIN_BATCH(1);
- OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16 | 0);
+ OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | 0);
ADVANCE_BATCH();
if (brw->gen < 6) {
@@ -926,8 +930,10 @@ brw_upload_invariant_state(struct brw_context *brw)
ADVANCE_BATCH();
}
+ const uint32_t _3DSTATE_VF_STATISTICS =
+ is_965 ? GEN4_3DSTATE_VF_STATISTICS : GM45_3DSTATE_VF_STATISTICS;
BEGIN_BATCH(1);
- OUT_BATCH(brw->CMD_VF_STATISTICS << 16 |
+ OUT_BATCH(_3DSTATE_VF_STATISTICS << 16 |
(unlikely(INTEL_DEBUG & DEBUG_STATS) ? 1 : 0));
ADVANCE_BATCH();
}