diff options
| -rw-r--r-- | src/gallium/drivers/radeon/r600_pipe_common.h | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/r600_texture.c | 11 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_blit.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 5 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 2 |
5 files changed, 16 insertions, 14 deletions
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h index 6eaa87a26b1..eb823b2e700 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ b/src/gallium/drivers/radeon/r600_pipe_common.h @@ -959,6 +959,12 @@ r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler) (!stencil_sampler && tex->can_sample_z); } +static inline bool +vi_dcc_enabled(struct r600_texture *tex, unsigned level) +{ + return tex->dcc_offset && level < tex->surface.num_dcc_levels; +} + #define COMPUTE_DBG(rscreen, fmt, args...) \ do { \ if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \ diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index dbcfd58a4bc..3cf1bb76482 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -72,8 +72,8 @@ bool r600_prepare_for_dma_blit(struct r600_common_context *rctx, * src: Use the 3D path. DCC decompression is expensive. * dst: Use the 3D path to compress the pixels with DCC. */ - if ((rsrc->dcc_offset && src_level < rsrc->surface.num_dcc_levels) || - (rdst->dcc_offset && dst_level < rdst->surface.num_dcc_levels)) + if (vi_dcc_enabled(rsrc, src_level) || + vi_dcc_enabled(rdst, dst_level)) return false; /* CMASK as: @@ -1912,8 +1912,7 @@ void vi_dcc_disable_if_incompatible_format(struct r600_common_context *rctx, { struct r600_texture *rtex = (struct r600_texture *)tex; - if (rtex->dcc_offset && - level < rtex->surface.num_dcc_levels && + if (vi_dcc_enabled(rtex, level) && !vi_dcc_formats_compatible(tex->format, view_format)) if (!r600_texture_disable_dcc(rctx, (struct r600_texture*)tex)) rctx->decompress_dcc(&rctx->b, rtex); @@ -2485,7 +2484,7 @@ void vi_dcc_clear_level(struct r600_common_context *rctx, struct pipe_resource *dcc_buffer; uint64_t dcc_offset, clear_size; - assert(rtex->dcc_offset && level < rtex->surface.num_dcc_levels); + assert(vi_dcc_enabled(rtex, level)); if (rtex->dcc_separate_buffer) { dcc_buffer = &rtex->dcc_separate_buffer->b.b; @@ -2701,7 +2700,7 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx, } /* Try to clear DCC first, otherwise try CMASK. */ - if (tex->dcc_offset && tex->surface.num_dcc_levels) { + if (vi_dcc_enabled(tex, 0)) { uint32_t reset_value; bool clear_words_needed; diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index cdc9cafa280..a94804d6c25 100644 --- a/src/gallium/drivers/radeonsi/si_blit.c +++ b/src/gallium/drivers/radeonsi/si_blit.c @@ -427,8 +427,7 @@ static void si_blit_decompress_color(struct pipe_context *ctx, /* disable levels without DCC */ for (int i = first_level; i <= last_level; i++) { - if (!rtex->dcc_offset || - i >= rtex->surface.num_dcc_levels) + if (!vi_dcc_enabled(rtex, i)) level_mask &= ~(1 << i); } } else if (rtex->fmask.size) { @@ -1039,8 +1038,7 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx, * it's being overwritten anyway, clear it to uncompressed. * This is still the fastest codepath even with this clear. */ - if (dst->dcc_offset && - info->dst.level < dst->surface.num_dcc_levels) { + if (vi_dcc_enabled(dst, info->dst.level)) { /* TODO: Implement per-level DCC clears for GFX9. */ if (sctx->b.chip_class >= GFX9 && info->dst.resource->last_level != 0) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 5450dbe0dd8..f28202f20a8 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -404,7 +404,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, va += base_level_info->offset; } - if (tex->dcc_offset && first_level < tex->surface.num_dcc_levels) { + if (vi_dcc_enabled(tex, first_level)) { meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) + tex->dcc_offset; @@ -750,8 +750,7 @@ static void si_set_shader_image(struct si_context *ctx, struct r600_texture *tex = (struct r600_texture *)res; unsigned level = view->u.tex.level; unsigned width, height, depth; - bool uses_dcc = tex->dcc_offset && - level < tex->surface.num_dcc_levels; + bool uses_dcc = vi_dcc_enabled(tex, level); assert(!tex->is_depth); assert(tex->fmask.size == 0); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index d2a1f4bf85c..14138fbd982 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2638,7 +2638,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8; /* Set up DCC. */ - if (tex->dcc_offset && cb->base.u.tex.level < tex->surface.num_dcc_levels) { + if (vi_dcc_enabled(tex, cb->base.u.tex.level)) { bool is_msaa_resolve_dst = state->cbufs[0] && state->cbufs[0]->texture->nr_samples > 1 && state->cbufs[1] == &cb->base && |