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-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp39
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.h4
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_emit.cpp26
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_fp.cpp4
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp8
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp10
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_visitor.cpp35
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm.h2
9 files changed, 64 insertions, 66 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 8971272d3c3..bcb67271665 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -483,11 +483,11 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
case SHADER_OPCODE_LOG2:
case SHADER_OPCODE_SIN:
case SHADER_OPCODE_COS:
- return 1 * c->dispatch_width / 8;
+ return 1 * dispatch_width / 8;
case SHADER_OPCODE_POW:
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
- return 2 * c->dispatch_width / 8;
+ return 2 * dispatch_width / 8;
case SHADER_OPCODE_TEX:
case FS_OPCODE_TXB:
case SHADER_OPCODE_TXD:
@@ -901,7 +901,7 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
if (intel->gen < 6) {
inst->base_mrf = 2;
- inst->mlen = c->dispatch_width / 8;
+ inst->mlen = dispatch_width / 8;
}
return inst;
@@ -964,7 +964,7 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
inst = emit(opcode, dst, op0, reg_null_f);
inst->base_mrf = base_mrf;
- inst->mlen = 2 * c->dispatch_width / 8;
+ inst->mlen = 2 * dispatch_width / 8;
}
return inst;
}
@@ -977,7 +977,7 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
void
fs_visitor::setup_paramvalues_refs()
{
- if (c->dispatch_width != 8)
+ if (dispatch_width != 8)
return;
/* Set up the pointers to ParamValues now that that array is finalized. */
@@ -992,7 +992,7 @@ void
fs_visitor::assign_curb_setup()
{
c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
- if (c->dispatch_width == 8) {
+ if (dispatch_width == 8) {
c->prog_data.first_curbe_grf = c->nr_payload_regs;
} else {
c->prog_data.first_curbe_grf_16 = c->nr_payload_regs;
@@ -1273,7 +1273,7 @@ fs_visitor::compact_virtual_grfs()
bool
fs_visitor::remove_dead_constants()
{
- if (c->dispatch_width == 8) {
+ if (dispatch_width == 8) {
this->params_remap = ralloc_array(mem_ctx, int, c->prog_data.nr_params);
for (unsigned int i = 0; i < c->prog_data.nr_params; i++)
@@ -1367,7 +1367,7 @@ fs_visitor::setup_pull_constants()
if (c->prog_data.nr_params <= max_uniform_components)
return;
- if (c->dispatch_width == 16) {
+ if (dispatch_width == 16) {
fail("Pull constants not supported in 16-wide\n");
return;
}
@@ -1711,7 +1711,7 @@ fs_visitor::compute_to_mrf()
int mrf_high;
if (inst->dst.reg & BRW_MRF_COMPR4) {
mrf_high = mrf_low + 4;
- } else if (c->dispatch_width == 16 &&
+ } else if (dispatch_width == 16 &&
(!inst->force_uncompressed && !inst->force_sechalf)) {
mrf_high = mrf_low + 1;
} else {
@@ -1816,7 +1816,7 @@ fs_visitor::compute_to_mrf()
if (scan_inst->dst.reg & BRW_MRF_COMPR4) {
scan_mrf_high = scan_mrf_low + 4;
- } else if (c->dispatch_width == 16 &&
+ } else if (dispatch_width == 16 &&
(!scan_inst->force_uncompressed &&
!scan_inst->force_sechalf)) {
scan_mrf_high = scan_mrf_low + 1;
@@ -1867,7 +1867,7 @@ fs_visitor::remove_duplicate_mrf_writes()
bool progress = false;
/* Need to update the MRF tracking for compressed instructions. */
- if (c->dispatch_width == 16)
+ if (dispatch_width == 16)
return false;
memset(last_mrf_move, 0, sizeof(last_mrf_move));
@@ -1989,7 +1989,7 @@ fs_visitor::setup_payload_gen6()
if (barycentric_interp_modes & (1 << i)) {
c->barycentric_coord_reg[i] = c->nr_payload_regs;
c->nr_payload_regs += 2;
- if (c->dispatch_width == 16) {
+ if (dispatch_width == 16) {
c->nr_payload_regs += 2;
}
}
@@ -1999,7 +1999,7 @@ fs_visitor::setup_payload_gen6()
if (uses_depth) {
c->source_depth_reg = c->nr_payload_regs;
c->nr_payload_regs++;
- if (c->dispatch_width == 16) {
+ if (dispatch_width == 16) {
/* R28: interpolated depth if not 8-wide. */
c->nr_payload_regs++;
}
@@ -2008,7 +2008,7 @@ fs_visitor::setup_payload_gen6()
if (uses_depth) {
c->source_w_reg = c->nr_payload_regs;
c->nr_payload_regs++;
- if (c->dispatch_width == 16) {
+ if (dispatch_width == 16) {
/* R30: interpolated W if not 8-wide. */
c->nr_payload_regs++;
}
@@ -2033,7 +2033,7 @@ fs_visitor::run()
else
setup_payload_gen4();
- if (c->dispatch_width == 16) {
+ if (dispatch_width == 16) {
/* We have to do a compaction pass now, or the one at the end of
* execution will squash down where our prog_offset start needs
* to be.
@@ -2131,7 +2131,7 @@ fs_visitor::run()
generate_code();
- if (c->dispatch_width == 8) {
+ if (dispatch_width == 8) {
c->prog_data.reg_blocks = brw_register_blocks(grf_used);
} else {
c->prog_data.reg_blocks_16 = brw_register_blocks(grf_used);
@@ -2177,9 +2177,7 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
/* Now the main event: Visit the shader IR and generate our FS IR for it.
*/
- c->dispatch_width = 8;
-
- fs_visitor v(c, prog, shader);
+ fs_visitor v(c, prog, shader, 8);
if (!v.run()) {
prog->LinkStatus = false;
ralloc_strcat(&prog->InfoLog, v.fail_msg);
@@ -2191,8 +2189,7 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
}
if (intel->gen >= 5 && c->prog_data.nr_pull_params == 0) {
- c->dispatch_width = 16;
- fs_visitor v2(c, prog, shader);
+ fs_visitor v2(c, prog, shader, 16);
v2.import_uniforms(&v);
if (!v2.run()) {
perf_debug("16-wide shader failed to compile, falling back to "
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 7ec489e9432..221623156f5 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -185,7 +185,7 @@ class fs_visitor : public backend_visitor
public:
fs_visitor(struct brw_wm_compile *c, struct gl_shader_program *prog,
- struct brw_shader *shader);
+ struct brw_shader *shader, unsigned dispatch_width);
~fs_visitor();
fs_reg *variable_storage(ir_variable *var);
@@ -447,6 +447,8 @@ public:
int grf_used;
+ const unsigned dispatch_width; /**< 8 or 16 */
+
int force_uncompressed_stack;
int force_sechalf_stack;
};
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 29c73cf14c7..7fdf5267163 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -93,7 +93,7 @@ fs_visitor::generate_fb_write(fs_inst *inst)
if (this->dual_src_output.file != BAD_FILE)
msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
- else if (c->dispatch_width == 16)
+ else if (dispatch_width == 16)
msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
else
msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
@@ -101,7 +101,7 @@ fs_visitor::generate_fb_write(fs_inst *inst)
brw_pop_insn_state(p);
brw_fb_WRITE(p,
- c->dispatch_width,
+ dispatch_width,
inst->base_mrf,
implied_header,
msg_control,
@@ -133,7 +133,7 @@ fs_visitor::generate_pixel_xy(struct brw_reg dst, bool is_x)
deltas = brw_imm_v(0x11001100);
}
- if (c->dispatch_width == 16) {
+ if (dispatch_width == 16) {
dst = vec16(dst);
}
@@ -203,7 +203,7 @@ fs_visitor::generate_math1_gen6(fs_inst *inst,
BRW_MATH_DATA_VECTOR,
BRW_MATH_PRECISION_FULL);
- if (c->dispatch_width == 16) {
+ if (dispatch_width == 16) {
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
brw_math(p, sechalf(dst),
op,
@@ -227,7 +227,7 @@ fs_visitor::generate_math2_gen6(fs_inst *inst,
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_math2(p, dst, op, src0, src1);
- if (c->dispatch_width == 16) {
+ if (dispatch_width == 16) {
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1));
brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
@@ -250,7 +250,7 @@ fs_visitor::generate_math_gen4(fs_inst *inst,
BRW_MATH_DATA_VECTOR,
BRW_MATH_PRECISION_FULL);
- if (c->dispatch_width == 16) {
+ if (dispatch_width == 16) {
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
brw_math(p, sechalf(dst),
op,
@@ -282,7 +282,7 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
break;
}
- if (c->dispatch_width == 16)
+ if (dispatch_width == 16)
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
if (intel->gen >= 5) {
@@ -328,7 +328,7 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
/* Note that G45 and older determines shadow compare and dispatch width
* from message length for most messages.
*/
- assert(c->dispatch_width == 8);
+ assert(dispatch_width == 8);
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
if (inst->shadow_compare) {
assert(inst->mlen == 6);
@@ -731,10 +731,10 @@ fs_visitor::generate_code()
if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
if (shader) {
printf("Native code for fragment shader %d (%d-wide dispatch):\n",
- prog->Name, c->dispatch_width);
+ prog->Name, dispatch_width);
} else {
printf("Native code for fragment program %d (%d-wide dispatch):\n",
- c->fp->program.Base.Id, c->dispatch_width);
+ c->fp->program.Base.Id, dispatch_width);
}
}
@@ -807,7 +807,7 @@ fs_visitor::generate_code()
brw_set_predicate_inverse(p, inst->predicate_inverse);
brw_set_saturate(p, inst->saturate);
- if (inst->force_uncompressed || c->dispatch_width == 8) {
+ if (inst->force_uncompressed || dispatch_width == 8) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
} else if (inst->force_sechalf) {
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -833,7 +833,7 @@ fs_visitor::generate_code()
case BRW_OPCODE_MAD:
brw_set_access_mode(p, BRW_ALIGN_16);
- if (c->dispatch_width == 16) {
+ if (dispatch_width == 16) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_MAD(p, dst, src[0], src[1], src[2]);
brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -893,7 +893,7 @@ fs_visitor::generate_code()
assert(intel->gen == 6);
gen6_IF(p, inst->conditional_mod, src[0], src[1]);
} else {
- brw_IF(p, c->dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
+ brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
}
break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index 834f290a315..542d80a6b40 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -255,7 +255,7 @@ fs_visitor::emit_fragment_program_code()
emit(CMP(null, regoffset(src[0], i), fs_reg(0.0f),
BRW_CONDITIONAL_L));
- if (intel->gen < 6 && c->dispatch_width == 16)
+ if (intel->gen < 6 && dispatch_width == 16)
fail("Can't support (non-uniform) control flow on 16-wide");
emit(IF(BRW_PREDICATE_NORMAL));
emit(FS_OPCODE_DISCARD);
@@ -589,7 +589,7 @@ fs_visitor::setup_fp_regs()
fp_temp_regs[i] = fs_reg(this, glsl_type::vec4_type);
/* PROGRAM_STATE_VAR etc. */
- if (c->dispatch_width == 8) {
+ if (dispatch_width == 8) {
for (unsigned p = 0;
p < c->fp->program.Base.Parameters->NumParameters; p++) {
for (unsigned int i = 0; i < 4; i++) {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
index d7bb7213676..db8f39732d2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
@@ -280,10 +280,10 @@ fs_visitor::virtual_grf_interferes(int a, int b)
* so our second half values in g6 got overwritten in the first
* half.
*/
- if (c->dispatch_width == 16 && (this->pixel_x.reg == a ||
- this->pixel_x.reg == b ||
- this->pixel_y.reg == a ||
- this->pixel_y.reg == b)) {
+ if (dispatch_width == 16 && (this->pixel_x.reg == a ||
+ this->pixel_x.reg == b ||
+ this->pixel_y.reg == a ||
+ this->pixel_y.reg == b)) {
return start <= end;
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index e83193e24ff..a4fc03218a0 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -45,7 +45,7 @@ fs_visitor::assign_regs_trivial()
{
int hw_reg_mapping[this->virtual_grf_count + 1];
int i;
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
/* Note that compressed instructions require alignment to 2 registers. */
hw_reg_mapping[0] = ALIGN(this->first_non_payload_grf, reg_width);
@@ -216,7 +216,7 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
int payload_node_count,
int first_payload_node)
{
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
int loop_depth = 0;
int loop_end_ip = 0;
@@ -338,7 +338,7 @@ void
fs_visitor::setup_mrf_hack_interference(struct ra_graph *g, int first_mrf_node)
{
int mrf_count = BRW_MAX_GRF - GEN7_MRF_HACK_START;
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
/* Identify all the MRFs used in the program. */
bool mrf_used[mrf_count];
@@ -394,7 +394,7 @@ fs_visitor::assign_regs()
* registers it's allocating be contiguous physical pairs of regs
* for reg_width == 2.
*/
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
int hw_reg_mapping[this->virtual_grf_count];
int payload_node_count = (ALIGN(this->first_non_payload_grf, reg_width) /
reg_width);
@@ -458,7 +458,7 @@ fs_visitor::assign_regs()
if (reg == -1) {
fail("no register to spill\n");
- } else if (c->dispatch_width == 16) {
+ } else if (dispatch_width == 16) {
fail("Failure to register allocate. Reduce number of live scalar "
"values to avoid this.");
} else {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
index 11e985880f5..6b7c412f8e7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
@@ -239,7 +239,7 @@ instruction_scheduler::add_barrier_deps(schedule_node *n)
bool
instruction_scheduler::is_compressed(fs_inst *inst)
{
- return (v->c->dispatch_width == 16 &&
+ return (v->dispatch_width == 16 &&
!inst->force_uncompressed &&
!inst->force_sechalf);
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 5d94181d64d..58e759fe1b8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -110,7 +110,7 @@ fs_visitor::visit(ir_variable *ir)
if (ir->uniform_block != -1)
return;
- if (c->dispatch_width == 16) {
+ if (dispatch_width == 16) {
if (!variable_storage(ir)) {
fail("Failed to find uniform '%s' in 16-wide\n", ir->name);
}
@@ -381,7 +381,7 @@ fs_visitor::visit(ir_expression *ir)
* FINISHME: Emit just the MUL if we know an operand is small
* enough.
*/
- if (intel->gen >= 7 && c->dispatch_width == 16)
+ if (intel->gen >= 7 && dispatch_width == 16)
fail("16-wide explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D);
@@ -394,7 +394,7 @@ fs_visitor::visit(ir_expression *ir)
}
break;
case ir_binop_div:
- if (intel->gen >= 7 && c->dispatch_width == 16)
+ if (intel->gen >= 7 && dispatch_width == 16)
fail("16-wide INTDIV unsupported\n");
/* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
@@ -402,7 +402,7 @@ fs_visitor::visit(ir_expression *ir)
emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
break;
case ir_binop_mod:
- if (intel->gen >= 7 && c->dispatch_width == 16)
+ if (intel->gen >= 7 && dispatch_width == 16)
fail("16-wide INTDIV unsupported\n");
/* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
@@ -888,7 +888,7 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
{
int mlen = 0;
int base_mrf = 2;
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
bool header_present = false;
const int vector_elements =
ir->coordinate ? ir->coordinate->type->vector_elements : 0;
@@ -1005,7 +1005,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
{
int mlen = 0;
int base_mrf = 2;
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
bool header_present = false;
int offsets[3];
@@ -1036,7 +1036,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
mlen += reg_width;
break;
case ir_txd: {
- if (c->dispatch_width == 16)
+ if (dispatch_width == 16)
fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
/* Load dPdx and the coordinate together:
@@ -1149,7 +1149,7 @@ fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
0
};
- if (c->dispatch_width == 16) {
+ if (dispatch_width == 16) {
fail("rectangle scale uniform setup not supported on 16-wide\n");
return coordinate;
}
@@ -1615,7 +1615,7 @@ fs_visitor::emit_if_gen6(ir_if *ir)
void
fs_visitor::visit(ir_if *ir)
{
- if (intel->gen < 6 && c->dispatch_width == 16) {
+ if (intel->gen < 6 && dispatch_width == 16) {
fail("Can't support (non-uniform) control flow on 16-wide\n");
}
@@ -1658,7 +1658,7 @@ fs_visitor::visit(ir_loop *ir)
{
fs_reg counter = reg_undef;
- if (intel->gen < 6 && c->dispatch_width == 16) {
+ if (intel->gen < 6 && dispatch_width == 16) {
fail("Can't support (non-uniform) control flow on 16-wide\n");
}
@@ -1790,7 +1790,7 @@ fs_visitor::emit(fs_inst *inst)
void
fs_visitor::emit_dummy_fs()
{
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
/* Everyone's favorite color. */
emit(MOV(fs_reg(MRF, 2 + 0 * reg_width), fs_reg(1.0f)));
@@ -1911,7 +1911,7 @@ fs_visitor::emit_interpolation_setup_gen6()
void
fs_visitor::emit_color_write(int target, int index, int first_color_mrf)
{
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
fs_inst *inst;
fs_reg color = outputs[target];
fs_reg mrf;
@@ -1922,7 +1922,7 @@ fs_visitor::emit_color_write(int target, int index, int first_color_mrf)
color.reg_offset += index;
- if (c->dispatch_width == 8 || intel->gen >= 6) {
+ if (dispatch_width == 8 || intel->gen >= 6) {
/* SIMD8 write looks like:
* m + 0: r0
* m + 1: r1
@@ -1992,11 +1992,11 @@ fs_visitor::emit_fb_writes()
*/
int base_mrf = 1;
int nr = base_mrf;
- int reg_width = c->dispatch_width / 8;
+ int reg_width = dispatch_width / 8;
bool do_dual_src = this->dual_src_output.file != BAD_FILE;
bool src0_alpha_to_render_target = false;
- if (c->dispatch_width == 16 && do_dual_src) {
+ if (dispatch_width == 16 && do_dual_src) {
fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
do_dual_src = false;
}
@@ -2040,7 +2040,7 @@ fs_visitor::emit_fb_writes()
nr += reg_width;
if (c->source_depth_to_render_target) {
- if (intel->gen == 6 && c->dispatch_width == 16) {
+ if (intel->gen == 6 && dispatch_width == 16) {
/* For outputting oDepth on gen6, SIMD8 writes have to be
* used. This would require 8-wide moves of each half to
* message regs, kind of like pre-gen5 SIMD16 FB writes.
@@ -2175,7 +2175,8 @@ fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg)
}
fs_visitor::fs_visitor(struct brw_wm_compile *c, struct gl_shader_program *prog,
- struct brw_shader *shader)
+ struct brw_shader *shader, unsigned dispatch_width)
+ : dispatch_width(dispatch_width)
{
this->c = c;
this->p = &c->func;
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index b8d8df3e012..a5ebdddc732 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -93,8 +93,6 @@ struct brw_wm_compile {
GLuint runtime_check_aads_emit:1;
GLuint last_scratch;
-
- GLuint dispatch_width;
};
bool brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 18:43:56 +0000