diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_screen.c | 21 |
4 files changed, 30 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c index 76988bfda7b..7760cce687b 100644 --- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c +++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c @@ -244,7 +244,7 @@ brw_get_fast_clear_rect(const struct brw_context *brw, * alignment size returned by intel_get_non_msrt_mcs_alignment(), but * with X alignment multiplied by 16 and Y alignment multiplied by 32. */ - intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align); + intel_get_non_msrt_mcs_alignment(brw, mt, &x_align, &y_align); x_align *= 16; /* SKL+ line alignment requirement for Y-tiled are half those of the prior @@ -838,7 +838,7 @@ brw_get_resolve_rect(const struct brw_context *brw, * by a factor of 2. */ - intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align); + intel_get_non_msrt_mcs_alignment(brw, mt, &x_align, &y_align); if (brw->gen >= 9) { x_scaledown = x_align * 8; y_scaledown = y_align * 8; diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 26c297da176..8099ea717bb 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -144,7 +144,8 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format, * by half the block width, and Y coordinates by half the block height. */ void -intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree *mt, +intel_get_non_msrt_mcs_alignment(const struct brw_context *brw, + const struct intel_mipmap_tree *mt, unsigned *width_px, unsigned *height) { switch (mt->tiling) { @@ -156,6 +157,11 @@ intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree *mt, *height = 4; break; case I915_TILING_X: + /* The docs are somewhat confusing with the way the tables are displayed. + * However, it does clearly state: "MCS and Lossless compression is + * supported for TiledY/TileYs/TileYf non-MSRTs only." + */ + assert(brw->gen < 9); *width_px = 64 / mt->cpp; *height = 2; } @@ -1552,7 +1558,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, const mesa_format format = MESA_FORMAT_R_UINT32; unsigned block_width_px; unsigned block_height; - intel_get_non_msrt_mcs_alignment(mt, &block_width_px, &block_height); + intel_get_non_msrt_mcs_alignment(brw, mt, &block_width_px, &block_height); unsigned width_divisor = block_width_px * 4; unsigned height_divisor = block_height * 8; diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 7862152cd97..21e4718513b 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -663,7 +663,8 @@ struct intel_mipmap_tree }; void -intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree *mt, +intel_get_non_msrt_mcs_alignment(const struct brw_context *brw, + const struct intel_mipmap_tree *mt, unsigned *width_px, unsigned *height); bool diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index db9d94d3b34..878901ac1f9 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -516,7 +516,11 @@ intel_create_image(__DRIscreen *screen, int cpp; unsigned long pitch; - tiling = I915_TILING_X; + if (intelScreen->devinfo->gen >= 9) { + tiling = I915_TILING_Y; + } else { + tiling = I915_TILING_X; + } if (use & __DRI_IMAGE_USE_CURSOR) { if (width != 64 || height != 64) return NULL; @@ -1144,8 +1148,14 @@ intel_detect_swizzling(struct intel_screen *screen) drm_intel_bo *buffer; unsigned long flags = 0; unsigned long aligned_pitch; - uint32_t tiling = I915_TILING_X; uint32_t swizzle_mode = 0; + uint32_t tiling; + + if (screen->devinfo->gen >= 9) { + tiling = I915_TILING_Y; + } else { + tiling = I915_TILING_X; + } buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "swizzle test", 64, 64, 4, @@ -1571,7 +1581,12 @@ intelAllocateBuffer(__DRIscreen *screen, return NULL; /* The front and back buffers are color buffers, which are X tiled. */ - uint32_t tiling = I915_TILING_X; + uint32_t tiling; + if (intelScreen->devinfo->gen >= 9) { + tiling = I915_TILING_Y; + } else { + tiling = I915_TILING_X; + } unsigned long pitch; int cpp = format / 8; intelBuffer->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr, |