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-rw-r--r--src/mesa/drivers/dri/i965/brw_ir_fs.h9
-rw-r--r--src/mesa/drivers/dri/i965/brw_shader.h9
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp1
3 files changed, 10 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index c569bd473d7..cad371248c4 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -367,15 +367,6 @@ public:
uint8_t sources; /**< Number of fs_reg sources. */
- /**
- * Channel group from the hardware execution and predication mask that
- * should be applied to the instruction. The subset of channel enable
- * signals (calculated from the EU control flow and predication state)
- * given by [group, group + exec_size) will be used to mask GRF writes and
- * any other side effects of the instruction.
- */
- uint8_t group;
-
bool eot:1;
bool pi_noperspective:1; /**< Pixel interpolator noperspective flag */
};
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index b5af6ab841f..6b5ee3719a9 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -140,6 +140,15 @@ struct backend_instruction {
*/
uint8_t exec_size;
+ /**
+ * Channel group from the hardware execution and predication mask that
+ * should be applied to the instruction. The subset of channel enable
+ * signals (calculated from the EU control flow and predication state)
+ * given by [group, group + exec_size) will be used to mask GRF writes and
+ * any other side effects of the instruction.
+ */
+ uint8_t group;
+
uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
uint8_t mlen; /**< SEND message length */
int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 0bf423cf654..9a9890631c2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -55,6 +55,7 @@ vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst,
this->base_mrf = 0;
this->offset = 0;
this->exec_size = 8;
+ this->group = 0;
this->size_written = (dst.file == BAD_FILE ?
0 : this->exec_size * type_sz(dst.type));
this->annotation = NULL;