diff options
| -rw-r--r-- | src/gallium/drivers/freedreno/a2xx/fd2_emit.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a4xx/fd4_emit.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_emit.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a6xx/fd6_emit.c | 3 |
4 files changed, 8 insertions, 4 deletions
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_emit.c b/src/gallium/drivers/freedreno/a2xx/fd2_emit.c index dcf7ed10b54..ba136deb1d8 100644 --- a/src/gallium/drivers/freedreno/a2xx/fd2_emit.c +++ b/src/gallium/drivers/freedreno/a2xx/fd2_emit.c @@ -241,7 +241,8 @@ fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty) OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */ } - if (dirty & FD_DIRTY_SCISSOR) { + /* NOTE: scissor enabled bit is part of rasterizer state: */ + if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) { struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx); OUT_PKT3(ring, CP_SET_CONSTANT, 3); diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c index 13cb2c44375..b5b0309f80a 100644 --- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c +++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c @@ -626,7 +626,8 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring, OUT_RING(ring, rast->pc_prim_vtx_cntl2); } - if (dirty & FD_DIRTY_SCISSOR) { + /* NOTE: scissor enabled bit is part of rasterizer state: */ + if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) { struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx); OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2); diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c index bca8aebe50a..e3bf9e26ba4 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c @@ -601,7 +601,8 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring, COND(fragz && fp->frag_coord, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1)); } - if (dirty & FD_DIRTY_SCISSOR) { + /* NOTE: scissor enabled bit is part of rasterizer state: */ + if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) { struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx); OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c index 5a7a42af969..c3823d85437 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c @@ -673,7 +673,8 @@ fd6_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring, OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z)); } - if (dirty & FD_DIRTY_SCISSOR) { + /* NOTE: scissor enabled bit is part of rasterizer state: */ + if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) { struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx); OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2); |