diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 4 |
5 files changed, 8 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 3589bb92009..be772ae547b 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -2280,12 +2280,12 @@ fs_visitor::opt_register_renaming() if (depth == 0 && inst->dst.file == GRF && - alloc.sizes[inst->dst.reg] == inst->dst.width / 8 && + alloc.sizes[inst->dst.reg] == inst->exec_size / 8 && !inst->is_partial_write()) { if (remap[dst] == -1) { remap[dst] = dst; } else { - remap[dst] = alloc.allocate(inst->dst.width / 8); + remap[dst] = alloc.allocate(inst->exec_size / 8); inst->dst.reg = remap[dst]; progress = true; } @@ -2416,7 +2416,7 @@ fs_visitor::compute_to_mrf() /* Things returning more than one register would need us to * understand coalescing out more than one MOV at a time. */ - if (scan_inst->regs_written > scan_inst->dst.width / 8) + if (scan_inst->regs_written > scan_inst->exec_size / 8) break; /* SEND instructions can't have MRF as a destination. */ diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp index 29d1f2a6a57..29b46b96b8a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp @@ -179,7 +179,7 @@ static void create_copy_instr(const fs_builder &bld, fs_inst *inst, fs_reg src, bool negate) { int written = inst->regs_written; - int dst_width = inst->dst.width / 8; + int dst_width = inst->exec_size / 8; const fs_builder ubld = bld.group(inst->exec_size, inst->force_sechalf) .exec_all(inst->force_writemask_all); fs_inst *copy; diff --git a/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp b/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp index 2ad7079bdf8..149c0f0e217 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp @@ -196,7 +196,7 @@ fs_visitor::register_coalesce() continue; } reg_to_offset[offset] = inst->dst.reg_offset; - if (inst->src[0].width == 16) + if (inst->exec_size == 16) reg_to_offset[offset + 1] = inst->dst.reg_offset + 1; mov[offset] = inst; channels_remaining -= inst->regs_written; diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 9b91f47d264..d5ff1be1414 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -913,7 +913,7 @@ fs_visitor::emit_texture(ir_texture_opcode op, bld.emit(SHADER_OPCODE_INT_QUOTIENT, fixed_depth, depth, fs_reg(6)); fs_reg *fixed_payload = ralloc_array(mem_ctx, fs_reg, inst->regs_written); - int components = inst->regs_written / (dst.width / 8); + int components = inst->regs_written / (inst->exec_size / 8); for (int i = 0; i < components; i++) { if (i == 2) { fixed_payload[i] = fixed_depth; diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp index ee0add5d765..b49961fff68 100644 --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp @@ -1314,8 +1314,8 @@ fs_instruction_scheduler::choose_instruction_to_schedule() * single-result send is probably actually reducing register * pressure. */ - if (inst->regs_written <= inst->dst.width / 8 && - chosen_inst->regs_written > chosen_inst->dst.width / 8) { + if (inst->regs_written <= inst->exec_size / 8 && + chosen_inst->regs_written > chosen_inst->exec_size / 8) { chosen = n; continue; } else if (inst->regs_written > chosen_inst->regs_written) { |