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-rw-r--r--src/mesa/drivers/dri/i965/brw_bufmgr.c6
-rw-r--r--src/mesa/drivers/dri/i965/brw_bufmgr.h12
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c46
-rw-r--r--src/mesa/drivers/dri/i965/intel_screen.c24
4 files changed, 44 insertions, 44 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 66a2d4964a2..26f14233e70 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -374,9 +374,9 @@ brw_bo_alloc(struct brw_bufmgr *bufmgr,
}
struct brw_bo *
-brw_bo_alloc_tiled(struct brw_bufmgr *bufmgr, const char *name,
- int x, int y, int cpp, uint32_t tiling,
- uint32_t *pitch, unsigned flags)
+brw_bo_alloc_tiled_2d(struct brw_bufmgr *bufmgr, const char *name,
+ int x, int y, int cpp, uint32_t tiling,
+ uint32_t *pitch, unsigned flags)
{
uint64_t size;
uint32_t stride;
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index ec5eb4cd618..1c116c2c091 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -157,12 +157,12 @@ struct brw_bo *brw_bo_alloc(struct brw_bufmgr *bufmgr, const char *name,
* 'tiling_mode' field on return, as well as the pitch value, which
* may have been rounded up to accommodate for tiling restrictions.
*/
-struct brw_bo *brw_bo_alloc_tiled(struct brw_bufmgr *bufmgr,
- const char *name,
- int x, int y, int cpp,
- uint32_t tiling_mode,
- uint32_t *pitch,
- unsigned flags);
+struct brw_bo *brw_bo_alloc_tiled_2d(struct brw_bufmgr *bufmgr,
+ const char *name,
+ int x, int y, int cpp,
+ uint32_t tiling_mode,
+ uint32_t *pitch,
+ unsigned flags);
/** Takes a reference on a buffer object */
void brw_bo_reference(struct brw_bo *bo);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 28215497fe0..23ff1a53cbc 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -657,16 +657,16 @@ miptree_create(struct brw_context *brw,
if (format == MESA_FORMAT_S_UINT8) {
/* Align to size of W tile, 64x64. */
- mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "miptree",
- ALIGN(mt->total_width, 64),
- ALIGN(mt->total_height, 64),
- mt->cpp, mt->tiling, &mt->pitch,
- alloc_flags);
+ mt->bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "miptree",
+ ALIGN(mt->total_width, 64),
+ ALIGN(mt->total_height, 64),
+ mt->cpp, mt->tiling, &mt->pitch,
+ alloc_flags);
} else {
- mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "miptree",
- mt->total_width, mt->total_height,
- mt->cpp, mt->tiling, &mt->pitch,
- alloc_flags);
+ mt->bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "miptree",
+ mt->total_width, mt->total_height,
+ mt->cpp, mt->tiling, &mt->pitch,
+ alloc_flags);
}
if (layout_flags & MIPTREE_LAYOUT_FOR_SCANOUT)
@@ -707,9 +707,9 @@ intel_miptree_create(struct brw_context *brw,
mt->tiling = I915_TILING_X;
brw_bo_unreference(mt->bo);
- mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "miptree",
- mt->total_width, mt->total_height, mt->cpp,
- mt->tiling, &mt->pitch, alloc_flags);
+ mt->bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "miptree",
+ mt->total_width, mt->total_height, mt->cpp,
+ mt->tiling, &mt->pitch, alloc_flags);
}
mt->offset = 0;
@@ -1599,9 +1599,9 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
* Therefore one can pass the ISL dimensions in terms of bytes instead of
* trying to recalculate based on different format block sizes.
*/
- buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "ccs-miptree",
- buf->pitch, buf->size / buf->pitch,
- 1, I915_TILING_Y, &buf->pitch, alloc_flags);
+ buf->bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "ccs-miptree",
+ buf->pitch, buf->size / buf->pitch,
+ 1, I915_TILING_Y, &buf->pitch, alloc_flags);
if (!buf->bo) {
free(buf);
free(aux_state);
@@ -1733,10 +1733,10 @@ intel_gen7_hiz_buf_create(struct brw_context *brw,
hz_height = DIV_ROUND_UP(hz_qpitch * Z0, 2 * 8) * 8;
}
- buf->aux_base.bo = brw_bo_alloc_tiled(brw->bufmgr, "hiz",
- hz_width, hz_height, 1,
- I915_TILING_Y, &buf->aux_base.pitch,
- BO_ALLOC_FOR_RENDER);
+ buf->aux_base.bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "hiz",
+ hz_width, hz_height, 1,
+ I915_TILING_Y, &buf->aux_base.pitch,
+ BO_ALLOC_FOR_RENDER);
if (!buf->aux_base.bo) {
free(buf);
return NULL;
@@ -1823,10 +1823,10 @@ intel_gen8_hiz_buf_create(struct brw_context *brw,
hz_height = DIV_ROUND_UP(buf->aux_base.qpitch, 2 * 8) * 8 * Z0;
}
- buf->aux_base.bo = brw_bo_alloc_tiled(brw->bufmgr, "hiz",
- hz_width, hz_height, 1,
- I915_TILING_Y, &buf->aux_base.pitch,
- BO_ALLOC_FOR_RENDER);
+ buf->aux_base.bo = brw_bo_alloc_tiled_2d(brw->bufmgr, "hiz",
+ hz_width, hz_height, 1,
+ I915_TILING_Y, &buf->aux_base.pitch,
+ BO_ALLOC_FOR_RENDER);
if (!buf->aux_base.bo) {
free(buf);
return NULL;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index fec4feabaff..83b8a24509a 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -679,9 +679,9 @@ intel_create_image_common(__DRIscreen *dri_screen,
return NULL;
cpp = _mesa_get_format_bytes(image->format);
- image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
- width, tiled_height, cpp, tiling,
- &image->pitch, 0);
+ image->bo = brw_bo_alloc_tiled_2d(screen->bufmgr, "image",
+ width, tiled_height, cpp, tiling,
+ &image->pitch, 0);
if (image->bo == NULL) {
free(image);
return NULL;
@@ -1500,8 +1500,8 @@ intel_detect_swizzling(struct intel_screen *screen)
uint32_t tiling = I915_TILING_X;
uint32_t swizzle_mode = 0;
- buffer = brw_bo_alloc_tiled(screen->bufmgr, "swizzle test",
- 64, 64, 4, tiling, &aligned_pitch, flags);
+ buffer = brw_bo_alloc_tiled_2d(screen->bufmgr, "swizzle test",
+ 64, 64, 4, tiling, &aligned_pitch, flags);
if (buffer == NULL)
return false;
@@ -2314,13 +2314,13 @@ intelAllocateBuffer(__DRIscreen *dri_screen,
* through to here. */
uint32_t pitch;
int cpp = format / 8;
- intelBuffer->bo = brw_bo_alloc_tiled(screen->bufmgr,
- "intelAllocateBuffer",
- width,
- height,
- cpp,
- I915_TILING_X, &pitch,
- BO_ALLOC_FOR_RENDER);
+ intelBuffer->bo = brw_bo_alloc_tiled_2d(screen->bufmgr,
+ "intelAllocateBuffer",
+ width,
+ height,
+ cpp,
+ I915_TILING_X, &pitch,
+ BO_ALLOC_FOR_RENDER);
if (intelBuffer->bo == NULL) {
free(intelBuffer);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 03:35:15 +0000