diff options
| -rw-r--r-- | src/amd/addrlib/addrinterface.h | 3 | ||||
| -rw-r--r-- | src/amd/addrlib/r800/ciaddrlib.cpp | 5 |
2 files changed, 7 insertions, 1 deletions
diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h index d94518fd769..bd10310dad2 100644 --- a/src/amd/addrlib/addrinterface.h +++ b/src/amd/addrlib/addrinterface.h @@ -2128,7 +2128,8 @@ typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT UINT_64 dccRamBaseAlign; ///< Base alignment of dcc key UINT_64 dccRamSize; ///< Size of dcc key UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared - BOOL_32 subLvlCompressible; ///< whether sub resource is compressiable + BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable + BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned } ADDR_COMPUTE_DCCINFO_OUTPUT; /** diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp index 776c8b5ce36..97ef3b6a8d1 100644 --- a/src/amd/addrlib/r800/ciaddrlib.cpp +++ b/src/amd/addrlib/r800/ciaddrlib.cpp @@ -247,6 +247,7 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeDccInfo( HwlGetPipes(&pIn->tileInfo) * m_pipeInterleaveBytes; pOut->dccFastClearSize = dccFastClearSize; + pOut->dccRamSizeAligned = TRUE; ADDR_ASSERT(IsPow2(pOut->dccRamBaseAlign)); @@ -262,6 +263,10 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeDccInfo( { pOut->dccFastClearSize = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign); } + if ((pOut->dccRamSize & (dccRamSizeAlign - 1)) != 0) + { + pOut->dccRamSizeAligned = FALSE; + } pOut->dccRamSize = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign); pOut->subLvlCompressible = FALSE; } |