diff options
| -rw-r--r-- | include/pci_ids/i965_pci_ids.h | 15 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_device_info.c | 29 |
2 files changed, 44 insertions, 0 deletions
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 2e04301fbb4..3e3e8fe4083 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -109,6 +109,21 @@ CHIPSET(0x162A, bdw_gt3, "Intel(R) Iris Pro P6300 (Broadwell GT3e)") CHIPSET(0x162B, bdw_gt3, "Intel(R) Iris 6100 (Broadwell GT3)") CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell GT3") CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell GT3") +CHIPSET(0x1902, skl_gt1, "Intel(R) Skylake DT GT1") +CHIPSET(0x1906, skl_gt1, "Intel(R) Skylake ULT GT1") +CHIPSET(0x190A, skl_gt1, "Intel(R) Skylake SRV GT1") +CHIPSET(0x190B, skl_gt1, "Intel(R) Skylake Halo GT1") +CHIPSET(0x190E, skl_gt1, "Intel(R) Skylake ULX GT1") +CHIPSET(0x1912, skl_gt2, "Intel(R) Skylake DT GT2") +CHIPSET(0x1916, skl_gt2, "Intel(R) Skylake ULT GT2") +CHIPSET(0x191A, skl_gt2, "Intel(R) Skylake SRV GT2") +CHIPSET(0x191B, skl_gt2, "Intel(R) Skylake Halo GT2") +CHIPSET(0x191D, skl_gt2, "Intel(R) Skylake WKS GT2") +CHIPSET(0x191E, skl_gt2, "Intel(R) Skylake ULX GT2") +CHIPSET(0x1921, skl_gt2, "Intel(R) Skylake ULT GT2F") +CHIPSET(0x1926, skl_gt3, "Intel(R) Skylake ULT GT3") +CHIPSET(0x192A, skl_gt3, "Intel(R) Skylake SRV GT3") +CHIPSET(0x192B, skl_gt3, "Intel(R) Skylake Halo GT3") CHIPSET(0x22B0, chv, "Intel(R) Cherryview") CHIPSET(0x22B1, chv, "Intel(R) Cherryview") CHIPSET(0x22B2, chv, "Intel(R) Cherryview") diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c index 35ca125b271..bbd907bf9e7 100644 --- a/src/mesa/drivers/dri/i965/brw_device_info.c +++ b/src/mesa/drivers/dri/i965/brw_device_info.c @@ -251,6 +251,35 @@ static const struct brw_device_info brw_device_info_chv = { } }; +/* Thread counts and URB limits are placeholders, and may not be accurate. */ +#define GEN9_FEATURES \ + .gen = 9, \ + .has_hiz_and_separate_stencil = true, \ + .must_use_separate_stencil = true, \ + .has_llc = true, \ + .has_pln = true, \ + .max_vs_threads = 280, \ + .max_gs_threads = 256, \ + .max_wm_threads = 408, \ + .urb = { \ + .size = 128, \ + .min_vs_entries = 64, \ + .max_vs_entries = 1664, \ + .max_gs_entries = 640, \ + } + +static const struct brw_device_info brw_device_info_skl_gt1 = { + GEN9_FEATURES, .gt = 1 +}; + +static const struct brw_device_info brw_device_info_skl_gt2 = { + GEN9_FEATURES, .gt = 2 +}; + +static const struct brw_device_info brw_device_info_skl_gt3 = { + GEN9_FEATURES, .gt = 3 +}; + const struct brw_device_info * brw_get_device_info(int devid) { |