diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.cpp | 37 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.h | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 4 |
3 files changed, 37 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index d6d00e718a8..afb453001d4 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -53,23 +53,52 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt, } void -brw_blorp_surface_info::set(struct intel_mipmap_tree *mt, +brw_blorp_surface_info::set(struct brw_context *brw, + struct intel_mipmap_tree *mt, unsigned int level, unsigned int layer) { brw_blorp_mip_info::set(mt, level, layer); this->num_samples = mt->num_samples; this->array_spacing_lod0 = mt->array_spacing_lod0; + this->map_stencil_as_y_tiled = false; - if (mt->format == MESA_FORMAT_S8) { + switch (mt->format) { + case MESA_FORMAT_S8: /* The miptree is a W-tiled stencil buffer. Surface states can't be set * up for W tiling, so we'll need to use Y tiling and have the WM * program swizzle the coordinates. */ this->map_stencil_as_y_tiled = true; this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM; - } else { - this->map_stencil_as_y_tiled = false; + break; + case MESA_FORMAT_X8_Z24: + case MESA_FORMAT_Z32_FLOAT: + /* The miptree consists of 32 bits per pixel, arranged either as 24-bit + * depth values interleaved with 8 "don't care" bits, or as 32-bit + * floating point depth values. Since depth values don't require any + * blending, it doesn't matter how we interpret the bit pattern as long + * as we copy the right amount of data, so just map it as 8-bit BGRA. + */ this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; + break; + case MESA_FORMAT_Z16: + /* The miptree consists of 16 bits per pixel of depth data. Since depth + * values don't require any blending, it doesn't matter how we interpret + * the bit pattern as long as we copy the right amount of data, so just + * map is as 8-bit RG. + */ + this->brw_surfaceformat = BRW_SURFACEFORMAT_R8G8_UNORM; + break; + default: + /* Blorp blits don't support any sort of format conversion, so we can + * safely assume that the same format is being used for the source and + * destination. Therefore the format must be supported as a render + * target, even if this is the source image. So we can convert to a + * surface format using brw->render_target_format. + */ + assert(brw->format_supported_as_render_target[mt->format]); + this->brw_surfaceformat = brw->render_target_format[mt->format]; + break; } } diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index 0de3d1e5d24..4c74c91e3a1 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -66,7 +66,8 @@ class brw_blorp_surface_info : public brw_blorp_mip_info public: brw_blorp_surface_info(); - void set(struct intel_mipmap_tree *mt, +void set(struct brw_context *brw, + struct intel_mipmap_tree *mt, unsigned int level, unsigned int layer); /* Setting this flag indicates that the buffer's contents are W-tiled diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index 93c3f73c1e7..180468b20a6 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -1274,8 +1274,8 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw, GLuint dst_x1, GLuint dst_y1, bool mirror_x, bool mirror_y) { - src.set(src_mt, 0, 0); - dst.set(dst_mt, 0, 0); + src.set(brw, src_mt, 0, 0); + dst.set(brw, dst_mt, 0, 0); use_wm_prog = true; memset(&wm_prog_key, 0, sizeof(wm_prog_key)); |