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-rw-r--r--src/intel/vulkan/gen7_cmd_buffer.c3
-rw-r--r--src/intel/vulkan/gen7_pipeline.c1
-rw-r--r--src/intel/vulkan/gen8_cmd_buffer.c3
-rw-r--r--src/intel/vulkan/gen8_pipeline.c1
4 files changed, 2 insertions, 6 deletions
diff --git a/src/intel/vulkan/gen7_cmd_buffer.c b/src/intel/vulkan/gen7_cmd_buffer.c
index 1713cc17836..71010583129 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -581,9 +581,6 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
- .StencilBufferWriteEnable = d->stencil_write_mask.front != 0 ||
- d->stencil_write_mask.back != 0,
-
.StencilTestMask = d->stencil_compare_mask.front & 0xff,
.StencilWriteMask = d->stencil_write_mask.front & 0xff,
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c
index 22a892bba3a..d563a8c26cd 100644
--- a/src/intel/vulkan/gen7_pipeline.c
+++ b/src/intel/vulkan/gen7_pipeline.c
@@ -95,6 +95,7 @@ gen7_emit_ds_state(struct anv_pipeline *pipeline,
.DoubleSidedStencilEnable = true,
.StencilTestEnable = info->stencilTestEnable,
+ .StencilBufferWriteEnable = info->stencilTestEnable,
.StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c
index d506cf48b0d..8e7a078d84b 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -384,9 +384,6 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
GENX(3DSTATE_WM_DEPTH_STENCIL_header),
- .StencilBufferWriteEnable = d->stencil_write_mask.front != 0 ||
- d->stencil_write_mask.back != 0,
-
.StencilTestMask = d->stencil_compare_mask.front & 0xff,
.StencilWriteMask = d->stencil_write_mask.front & 0xff,
diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c
index ecb8f6d7b09..e8a067851cc 100644
--- a/src/intel/vulkan/gen8_pipeline.c
+++ b/src/intel/vulkan/gen8_pipeline.c
@@ -227,6 +227,7 @@ emit_ds_state(struct anv_pipeline *pipeline,
.DoubleSidedStencilEnable = true,
.StencilTestEnable = info->stencilTestEnable,
+ .StencilBufferWriteEnable = info->stencilTestEnable,
.StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],