diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.c | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_depth_state.c | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 18 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 |
5 files changed, 8 insertions, 28 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 94845746d25..60ae8407911 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -123,8 +123,7 @@ apply_gen6_stencil_hiz_offset(struct isl_surf *surf, } else { *offset = intel_miptree_get_aligned_offset(mt, mt->level[lod].level_x, - mt->level[lod].level_y, - false); + mt->level[lod].level_y); } surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod); diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index cc62dab363f..6fce0389397 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -451,14 +451,12 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw, brw->depthstencil.depth_offset = intel_miptree_get_aligned_offset(depth_mt, depth_irb->draw_x & ~tile_mask_x, - depth_irb->draw_y & ~tile_mask_y, - false); + depth_irb->draw_y & ~tile_mask_y); if (intel_renderbuffer_has_hiz(depth_irb)) { brw->depthstencil.hiz_offset = intel_miptree_get_aligned_offset(depth_mt, depth_irb->draw_x & ~tile_mask_x, - (depth_irb->draw_y & ~tile_mask_y) / 2, - false); + (depth_irb->draw_y & ~tile_mask_y) / 2); } } if (stencil_irb) { diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c index 1a29860580d..3f14006f8a6 100644 --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c @@ -168,8 +168,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, offset = intel_miptree_get_aligned_offset( hiz_mt, hiz_mt->level[lod].level_x, - hiz_mt->level[lod].level_y, - false); + hiz_mt->level[lod].level_y); } BEGIN_BATCH(3); @@ -204,8 +203,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw, offset = intel_miptree_get_aligned_offset( stencil_mt, stencil_mt->level[lod].level_x, - stencil_mt->level[lod].level_y, - false); + stencil_mt->level[lod].level_y); } } diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index aba203abac6..866d61f7062 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -1266,26 +1266,12 @@ intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp, */ uint32_t intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt, - uint32_t x, uint32_t y, - bool map_stencil_as_y_tiled) + uint32_t x, uint32_t y) { int cpp = mt->cpp; uint32_t pitch = mt->pitch; uint32_t tiling = mt->tiling; - if (map_stencil_as_y_tiled) { - tiling = I915_TILING_Y; - - /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile - * gets transformed into a 32-high Y-tile. Accordingly, the pitch of - * the resulting surface is twice the pitch of the original miptree, - * since each row in the Y-tiled view corresponds to two rows in the - * actual W-tiled surface. So we need to correct the pitch before - * computing the offsets. - */ - pitch *= 2; - } - switch (tiling) { default: unreachable("not reached"); @@ -1327,7 +1313,7 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, *tile_x = x & mask_x; *tile_y = y & mask_y; - return intel_miptree_get_aligned_offset(mt, x & ~mask_x, y & ~mask_y, false); + return intel_miptree_get_aligned_offset(mt, x & ~mask_x, y & ~mask_y); } static void diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 2f1b8ebf0e1..f26a6b0f5d8 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -846,8 +846,7 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, uint32_t *tile_y); uint32_t intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt, - uint32_t x, uint32_t y, - bool map_stencil_as_y_tiled); + uint32_t x, uint32_t y); void intel_miptree_set_level_info(struct intel_mipmap_tree *mt, GLuint level, |