diff options
| -rw-r--r-- | src/intel/compiler/brw_compiler.c | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_program.c | 4 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 4101f99d992..4fa02ca4d10 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -206,7 +206,6 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo) nir_options->lower_doubles_options = fp64_options; compiler->glsl_compiler_options[i].NirOptions = nir_options; - compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true; compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true; } diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 4f9b7aa71d7..2ef11508c79 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -121,6 +121,10 @@ brw_create_nir(struct brw_context *brw, NIR_PASS_V(nir, brw_nir_lower_image_load_store, devinfo); + NIR_PASS_V(nir, gl_nir_lower_buffers, shader_prog); + /* Do a round of constant folding to clean up address calculations */ + NIR_PASS_V(nir, nir_opt_constant_folding); + if (stage == MESA_SHADER_TESS_CTRL) { /* Lower gl_PatchVerticesIn from a sys. value to a uniform on Gen8+. */ static const gl_state_index16 tokens[STATE_LENGTH] = |