diff options
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 3 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 5 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_extensions.py | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 3 |
6 files changed, 7 insertions, 8 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index ec7b74aaaf4..6c91a5bd848 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -457,6 +457,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, info->has_rbplus = info->family == CHIP_STONEY || info->chip_class >= GFX9; + info->has_out_of_order_rast = info->chip_class >= GFX8 && + info->max_se >= 2; + /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */ info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 || (info->chip_class >= GFX8 && diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 10a3205f44d..ea6b9111108 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -63,6 +63,7 @@ struct radeon_info { bool has_dcc_constant_encode; bool has_rbplus; /* if RB+ registers exist */ bool has_load_ctx_reg_pkt; + bool has_out_of_order_rast; /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index e49fbe36270..5406ec72239 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -371,10 +371,7 @@ radv_physical_device_init(struct radv_physical_device *device, device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10; - /* Out-of-order primitive rasterization. */ - device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 && - device->rad_info.max_se >= 2; - device->out_of_order_rast_allowed = device->has_out_of_order_rast && + device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast && !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER); device->dcc_msaa_allowed = diff --git a/src/amd/vulkan/radv_extensions.py b/src/amd/vulkan/radv_extensions.py index b349ab74d58..34d63ed90c3 100644 --- a/src/amd/vulkan/radv_extensions.py +++ b/src/amd/vulkan/radv_extensions.py @@ -140,7 +140,7 @@ EXTENSIONS = [ Extension('VK_AMD_gcn_shader', 1, True), Extension('VK_AMD_gpu_shader_half_float', 1, 'device->rad_info.chip_class >= GFX9'), Extension('VK_AMD_gpu_shader_int16', 1, 'device->rad_info.chip_class >= GFX9'), - Extension('VK_AMD_rasterization_order', 1, 'device->has_out_of_order_rast'), + Extension('VK_AMD_rasterization_order', 1, 'device->rad_info.has_out_of_order_rast'), Extension('VK_AMD_shader_ballot', 1, 'device->use_shader_ballot'), Extension('VK_AMD_shader_core_properties', 1, True), Extension('VK_AMD_shader_core_properties2', 1, True), diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index f252270b207..380e2a8e632 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -285,7 +285,6 @@ struct radv_physical_device { bool has_scissor_bug; bool has_tc_compat_zrange_bug; - bool has_out_of_order_rast; bool out_of_order_rast_allowed; /* Whether DCC should be enabled for MSAA textures. */ diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 525202c7c20..49fb3cac951 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1121,8 +1121,7 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws, sscreen->info.pfp_fw_version >= 79 && sscreen->info.me_fw_version >= 142); - sscreen->has_out_of_order_rast = sscreen->info.chip_class >= GFX8 && - sscreen->info.max_se >= 2 && + sscreen->has_out_of_order_rast = sscreen->info.has_out_of_order_rast && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER)); sscreen->assume_no_z_fights = driQueryOptionb(config->options, "radeonsi_assume_no_z_fights"); |