diff options
| -rw-r--r-- | src/gallium/drivers/radeon/r600_texture.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_winsys.h | 1 | ||||
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 13 |
3 files changed, 7 insertions, 10 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 789c66fd169..edfdfe33187 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -641,9 +641,8 @@ r600_texture_create_object(struct pipe_screen *screen, return NULL; } } - if (rtex->surface.dcc_enabled) { + if (rtex->surface.dcc_size) vi_texture_alloc_dcc_separate(rscreen, rtex); - } } /* Now create the backing buffer. */ diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index 0178643549e..8bf1e15f3be 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -371,7 +371,6 @@ struct radeon_surf { uint64_t dcc_size; uint64_t dcc_alignment; - bool dcc_enabled; }; struct radeon_bo_list_item { diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index b442174b7b8..3006bd17958 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -251,7 +251,7 @@ static int compute_level(struct amdgpu_winsys *ws, surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize; - if (surf->dcc_enabled) { + if (AddrSurfInfoIn->flags.dccCompatible) { AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize; AddrDccIn->tileMode = AddrSurfInfoOut->tileMode; AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo; @@ -267,10 +267,11 @@ static int compute_level(struct amdgpu_winsys *ws, surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize; surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign); } else { - surf->dcc_enabled = false; + surf->dcc_size = 0; surf_level->dcc_offset = 0; } } else { + surf->dcc_size = 0; surf_level->dcc_offset = 0; } @@ -354,10 +355,6 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf->nsamples; AddrSurfInfoIn.tileIndex = -1; - surf->dcc_enabled = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && - !(surf->flags & RADEON_SURF_SCANOUT) && - !compressed && AddrDccIn.numSamples <= 1; - /* Set the micro tile type. */ if (surf->flags & RADEON_SURF_SCANOUT) AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE; @@ -373,7 +370,9 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0; AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0; AddrSurfInfoIn.flags.degrade4Space = 1; - AddrSurfInfoIn.flags.dccCompatible = surf->dcc_enabled; + AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && + !(surf->flags & RADEON_SURF_SCANOUT) && + !compressed && AddrDccIn.numSamples <= 1; /* This disables incorrect calculations (hacks) in addrlib. */ AddrSurfInfoIn.flags.noStencil = 1; |