diff options
| -rw-r--r-- | src/amd/common/ac_surface.c | 4 | ||||
| -rw-r--r-- | src/amd/common/ac_surface.h | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 2 |
3 files changed, 6 insertions, 2 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 9cc2b932830..92aab57920a 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1062,8 +1062,10 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, surf->surf_alignment = out.baseAlign; if (in->swizzleMode == ADDR_SW_LINEAR) { - for (unsigned i = 0; i < in->numMipLevels; i++) + for (unsigned i = 0; i < in->numMipLevels; i++) { surf->u.gfx9.offset[i] = mip_info[i].offset; + surf->u.gfx9.pitch[i] = mip_info[i].pitch; + } } if (in->flags.depth) { diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index c838bd47da5..1e90c08b2e5 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -154,6 +154,8 @@ struct gfx9_surf_layout { uint64_t surf_slice_size; /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */ uint32_t offset[RADEON_SURF_MAX_LEVELS]; + /* Mipmap level pitch in elements. Only valid for LINEAR. */ + uint32_t pitch[RADEON_SURF_MAX_LEVELS]; uint64_t stencil_offset; /* separate stencil */ diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index deb34af3733..544a51f5f39 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1889,7 +1889,7 @@ void radv_GetImageSubresourceLayout( pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3; } else { assert(util_is_power_of_two_nonzero(surface->bpe)); - pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe; + pLayout->rowPitch = surface->u.gfx9.pitch[level] * surface->bpe; } pLayout->arrayPitch = surface->u.gfx9.surf_slice_size; |