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-rw-r--r--src/intel/blorp/blorp_clear.c12
-rw-r--r--src/intel/blorp/blorp_genX_exec.h6
2 files changed, 17 insertions, 1 deletions
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 982028dd49d..d7668eac3ca 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -898,7 +898,11 @@ blorp_ccs_resolve(struct blorp_batch *batch,
params.x1 = ALIGN(params.x1, x_scaledown) / x_scaledown;
params.y1 = ALIGN(params.y1, y_scaledown) / y_scaledown;
- if (batch->blorp->isl_dev->info->gen >= 9) {
+ if (batch->blorp->isl_dev->info->gen >= 10) {
+ assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
+ resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE ||
+ resolve_op == ISL_AUX_OP_AMBIGUATE);
+ } else if (batch->blorp->isl_dev->info->gen >= 9) {
assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
} else {
@@ -1057,6 +1061,12 @@ blorp_ccs_ambiguate(struct blorp_batch *batch,
struct blorp_surf *surf,
uint32_t level, uint32_t layer)
{
+ if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 10) {
+ /* On gen10 and above, we have a hardware resolve op for this */
+ return blorp_ccs_resolve(batch, surf, level, layer, 1,
+ surf->surf->format, ISL_AUX_OP_AMBIGUATE);
+ }
+
struct blorp_params params;
blorp_params_init(&params);
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 76a1208aa66..f3e64c56382 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -827,6 +827,12 @@ blorp_emit_ps_config(struct blorp_batch *batch,
switch (params->fast_clear_op) {
case ISL_AUX_OP_NONE:
break;
+#if GEN_GEN >= 10
+ case ISL_AUX_OP_AMBIGUATE:
+ ps.RenderTargetFastClearEnable = true;
+ ps.RenderTargetResolveType = FAST_CLEAR_0;
+ break;
+#endif
#if GEN_GEN >= 9
case ISL_AUX_OP_PARTIAL_RESOLVE:
ps.RenderTargetResolveType = RESOLVE_PARTIAL;