diff options
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 28 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 3 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_meta_clear.c | 3 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_meta_fast_clear.c | 7 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 4 |
5 files changed, 44 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index b4aea5bc898..982107138d3 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1059,6 +1059,11 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base); } } + + if (radv_image_has_dcc(image)) { + /* Drawing with DCC enabled also compresses colorbuffers. */ + radv_update_dcc_metadata(cmd_buffer, image, true); + } } static void @@ -1387,6 +1392,29 @@ radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer, } /** + * Update the DCC predicate to reflect the compression state. + */ +void +radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer, + struct radv_image *image, bool value) +{ + uint64_t pred_val = value; + uint64_t va = radv_buffer_get_va(image->bo); + va += image->offset + image->dcc_pred_offset; + + assert(radv_image_has_dcc(image)); + + radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0)); + radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) | + S_370_WR_CONFIRM(1) | + S_370_ENGINE_SEL(V_370_PFP)); + radeon_emit(cmd_buffer->cs, va); + radeon_emit(cmd_buffer->cs, va >> 32); + radeon_emit(cmd_buffer->cs, pred_val); + radeon_emit(cmd_buffer->cs, pred_val >> 32); +} + +/** * Update the fast clear color values if the image is bound as a color buffer. */ static void diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 090ca70a327..79e9ada011a 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -858,7 +858,8 @@ radv_image_alloc_dcc(struct radv_image *image) /* + 16 for storing the clear values + dcc pred */ image->clear_value_offset = image->dcc_offset + image->surface.dcc_size; image->fce_pred_offset = image->clear_value_offset + 8; - image->size = image->dcc_offset + image->surface.dcc_size + 16; + image->dcc_pred_offset = image->clear_value_offset + 16; + image->size = image->dcc_offset + image->surface.dcc_size + 24; image->alignment = MAX2(image->alignment, image->surface.dcc_alignment); } diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 83d4b071d52..3f9f0a22750 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1288,6 +1288,9 @@ uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, uint32_t value) { + /* Mark the image as being compressed. */ + radv_update_dcc_metadata(cmd_buffer, image, true); + return radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset, image->surface.dcc_size, value); diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index f2f68961e2e..481c432513f 100644 --- a/src/amd/vulkan/radv_meta_fast_clear.c +++ b/src/amd/vulkan/radv_meta_fast_clear.c @@ -706,6 +706,10 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer, * FMASK and DCC also imply a fast-clear eliminate. */ radv_update_fce_metadata(cmd_buffer, image, false); + + /* Mark the image as being decompressed. */ + if (decompress_dcc) + radv_update_dcc_metadata(cmd_buffer, image, false); } radv_meta_restore(&saved_state, cmd_buffer); @@ -802,6 +806,9 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, radv_unaligned_dispatch(cmd_buffer, image->info.width, image->info.height, 1); + /* Mark this image as actually being decompressed. */ + radv_update_dcc_metadata(cmd_buffer, image, false); + /* The fill buffer below does its own saving */ radv_meta_restore(&saved_state, cmd_buffer); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index e3dd301ee8f..9a9cd5ff935 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1206,6 +1206,9 @@ void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, bool value); +void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer, + struct radv_image *image, bool value); + uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size, uint32_t value); @@ -1502,6 +1505,7 @@ struct radv_image { struct radv_cmask_info cmask; uint64_t clear_value_offset; uint64_t fce_pred_offset; + uint64_t dcc_pred_offset; /* * Metadata for the TC-compat zrange workaround. If the 32-bit value |