diff options
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 7 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 12 |
2 files changed, 8 insertions, 11 deletions
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 85ba165b4c6..9bdad6ad6fd 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -2983,6 +2983,7 @@ radv_initialise_color_surface(struct radv_device *device, S_028C74_PIPE_ALIGNED(meta.pipe_aligned); cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8; + cb->cb_color_base |= iview->image->surface.tile_swizzle; } else { const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip]; unsigned pitch_tile_max, slice_tile_max, tile_mode_index; @@ -3024,8 +3025,7 @@ radv_initialise_color_surface(struct radv_device *device, va = device->ws->buffer_get_va(iview->bo) + iview->image->offset; va += iview->image->dcc_offset; cb->cb_dcc_base = va >> 8; - if (device->physical_device->rad_info.chip_class < GFX9) - cb->cb_dcc_base |= iview->image->surface.tile_swizzle; + cb->cb_dcc_base |= iview->image->surface.tile_swizzle; uint32_t max_slice = radv_surface_layer_count(iview); cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) | @@ -3041,8 +3041,7 @@ radv_initialise_color_surface(struct radv_device *device, if (iview->image->fmask.size) { va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset; cb->cb_color_fmask = va >> 8; - if (device->physical_device->rad_info.chip_class < GFX9) - cb->cb_color_fmask |= iview->image->fmask.tile_swizzle; + cb->cb_color_fmask |= iview->image->fmask.tile_swizzle; } else { cb->cb_color_fmask = cb->cb_color_base; } diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 7a4b2d57a51..314964d64e5 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -215,9 +215,9 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, va += base_level_info->offset; state[0] = va >> 8; - if (chip_class < GFX9) - if (base_level_info->mode == RADEON_SURF_MODE_2D) - state[0] |= image->surface.tile_swizzle; + if (chip_class >= GFX9 || + base_level_info->mode == RADEON_SURF_MODE_2D) + state[0] |= image->surface.tile_swizzle; state[1] &= C_008F14_BASE_ADDRESS_HI; state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40); @@ -230,8 +230,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, meta_va += base_level_info->dcc_offset; state[6] |= S_008F28_COMPRESSION_EN(1); state[7] = meta_va >> 8; - if (chip_class < GFX9) - state[7] |= image->surface.tile_swizzle; + state[7] |= image->surface.tile_swizzle; } } @@ -479,8 +478,7 @@ si_make_texture_descriptor(struct radv_device *device, } fmask_state[0] = va >> 8; - if (device->physical_device->rad_info.chip_class < GFX9) - fmask_state[0] |= image->fmask.tile_swizzle; + fmask_state[0] |= image->fmask.tile_swizzle; fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) | S_008F14_DATA_FORMAT_GFX6(fmask_format) | S_008F14_NUM_FORMAT_GFX6(num_format); |