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-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c8
-rw-r--r--src/mesa/drivers/dri/i965/intel_fbo.c2
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c16
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.h8
-rw-r--r--src/mesa/drivers/dri/i965/intel_tex.c2
-rw-r--r--src/mesa/drivers/dri/i965/intel_tex_image.c2
-rw-r--r--src/mesa/drivers/dri/i965/intel_tex_validate.c2
7 files changed, 20 insertions, 20 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index fb78b08b649..c9ee5265a1d 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -630,12 +630,12 @@ brw_miptree_choose_tiling(struct brw_context *brw,
/* Some usages may want only one type of tiling, like depth miptrees (Y
* tiled), or temporary BOs for uploading data once (linear).
*/
- switch (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) {
- case MIPTREE_LAYOUT_ALLOC_ANY_TILED:
+ switch (layout_flags & MIPTREE_LAYOUT_TILING_ANY) {
+ case MIPTREE_LAYOUT_TILING_ANY:
break;
- case MIPTREE_LAYOUT_ALLOC_YTILED:
+ case MIPTREE_LAYOUT_TILING_Y:
return I915_TILING_Y;
- case MIPTREE_LAYOUT_ALLOC_LINEAR:
+ case MIPTREE_LAYOUT_TILING_NONE:
return I915_TILING_NONE;
}
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 87ba624b70d..72648b01e33 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -1023,7 +1023,7 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
int width, height, depth;
uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
- MIPTREE_LAYOUT_ALLOC_ANY_TILED;
+ MIPTREE_LAYOUT_TILING_ANY;
intel_miptree_get_dimensions_for_image(rb->TexImage, &width, &height, &depth);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index cb2791db02f..e85c3f00c7b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -455,7 +455,7 @@ intel_miptree_create_layout(struct brw_context *brw,
uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
if (brw->gen == 6) {
stencil_flags |= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD |
- MIPTREE_LAYOUT_ALLOC_ANY_TILED;
+ MIPTREE_LAYOUT_TILING_ANY;
}
mt->stencil_mt = intel_miptree_create(brw,
@@ -759,8 +759,8 @@ intel_miptree_create_for_bo(struct brw_context *brw,
/* The BO already has a tiling format and we shouldn't confuse the lower
* layers by making it try to find a tiling format again.
*/
- assert((layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) == 0);
- assert((layout_flags & MIPTREE_LAYOUT_ALLOC_LINEAR) == 0);
+ assert((layout_flags & MIPTREE_LAYOUT_TILING_ANY) == 0);
+ assert((layout_flags & MIPTREE_LAYOUT_TILING_NONE) == 0);
layout_flags |= MIPTREE_LAYOUT_FOR_BO;
mt = intel_miptree_create_layout(brw, target, format,
@@ -874,7 +874,7 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw,
bool ok;
GLenum target = num_samples > 1 ? GL_TEXTURE_2D_MULTISAMPLE : GL_TEXTURE_2D;
const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
- MIPTREE_LAYOUT_ALLOC_ANY_TILED;
+ MIPTREE_LAYOUT_TILING_ANY;
mt = intel_miptree_create(brw, target, format, 0, 0,
@@ -1385,7 +1385,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
* "The MCS surface must be stored as Tile Y."
*/
const uint32_t mcs_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
- MIPTREE_LAYOUT_ALLOC_YTILED;
+ MIPTREE_LAYOUT_TILING_Y;
mt->mcs_mt = intel_miptree_create(brw,
mt->target,
format,
@@ -1444,7 +1444,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
ALIGN(mt->logical_height0, height_divisor) / height_divisor;
assert(mt->logical_depth0 == 1);
uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
- MIPTREE_LAYOUT_ALLOC_YTILED;
+ MIPTREE_LAYOUT_TILING_Y;
if (brw->gen >= 8) {
layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
}
@@ -1709,7 +1709,7 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
if (!buf)
return NULL;
- layout_flags |= MIPTREE_LAYOUT_ALLOC_ANY_TILED;
+ layout_flags |= MIPTREE_LAYOUT_TILING_ANY;
buf->mt = intel_miptree_create(brw,
mt->target,
mt->format,
@@ -2149,7 +2149,7 @@ intel_miptree_map_blit(struct brw_context *brw,
map->mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format,
0, 0,
map->w, map->h, 1,
- 0, MIPTREE_LAYOUT_ALLOC_LINEAR);
+ 0, MIPTREE_LAYOUT_TILING_NONE);
if (!map->mt) {
fprintf(stderr, "Failed to allocate blit temporary\n");
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 506c25846cf..790d3129207 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -536,10 +536,10 @@ enum {
MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3,
MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4,
- MIPTREE_LAYOUT_ALLOC_YTILED = 1 << 5,
- MIPTREE_LAYOUT_ALLOC_LINEAR = 1 << 6,
- MIPTREE_LAYOUT_ALLOC_ANY_TILED = MIPTREE_LAYOUT_ALLOC_YTILED |
- MIPTREE_LAYOUT_ALLOC_LINEAR,
+ MIPTREE_LAYOUT_TILING_Y = 1 << 5,
+ MIPTREE_LAYOUT_TILING_NONE = 1 << 6,
+ MIPTREE_LAYOUT_TILING_ANY = MIPTREE_LAYOUT_TILING_Y |
+ MIPTREE_LAYOUT_TILING_NONE,
};
struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c
index 8fa5e3cd55a..e16b0def0d4 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -145,7 +145,7 @@ intel_alloc_texture_storage(struct gl_context *ctx,
0, levels - 1,
width, height, depth,
num_samples,
- MIPTREE_LAYOUT_ALLOC_ANY_TILED);
+ MIPTREE_LAYOUT_TILING_ANY);
if (intel_texobj->mt == NULL) {
return false;
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 3611280012e..93a8cdee0cb 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -80,7 +80,7 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
height,
depth,
intelImage->base.Base.NumSamples,
- layout_flags | MIPTREE_LAYOUT_ALLOC_ANY_TILED);
+ layout_flags | MIPTREE_LAYOUT_TILING_ANY);
}
static void
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index 6ebf381e626..d3fb252b5d5 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -137,7 +137,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
width, height, depth, validate_last_level + 1);
const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
- MIPTREE_LAYOUT_ALLOC_ANY_TILED;
+ MIPTREE_LAYOUT_TILING_ANY;
intelObj->mt = intel_miptree_create(brw,
intelObj->base.Target,
firstImage->base.Base.TexFormat,
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 02:58:19 +0000