diff options
| -rw-r--r-- | src/intel/isl/isl.c | 47 | ||||
| -rw-r--r-- | src/intel/isl/isl.h | 14 | ||||
| -rw-r--r-- | src/intel/isl/isl_format_layout.csv | 9 | ||||
| -rw-r--r-- | src/intel/isl/isl_gen7.c | 7 | ||||
| -rw-r--r-- | src/intel/isl/isl_gen8.c | 13 | ||||
| -rw-r--r-- | src/intel/isl/isl_gen9.c | 12 |
6 files changed, 102 insertions, 0 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 7df649eff0a..48ff8ce15c5 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -177,6 +177,29 @@ isl_tiling_get_info(const struct isl_device *dev, phys_B = isl_extent2d(128, 32); break; + case ISL_TILING_CCS: + /* CCS surfaces are required to have one of the GENX_CCS_* formats which + * have a block size of 1 or 2 bits per block and each CCS element + * corresponds to one cache-line pair in the main surface. From the Sky + * Lake PRM Vol. 12 in the section on planes: + * + * "The Color Control Surface (CCS) contains the compression status + * of the cache-line pairs. The compression state of the cache-line + * pair is specified by 2 bits in the CCS. Each CCS cache-line + * represents an area on the main surface of 16x16 sets of 128 byte + * Y-tiled cache-line-pairs. CCS is always Y tiled." + * + * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines. + * Since each cache line corresponds to a 16x16 set of cache-line pairs, + * that yields total tile area of 128x128 cache-line pairs or CCS + * elements. On older hardware, each CCS element is 1 bit and the tile + * is 128x256 elements. + */ + assert(format_bpb == 1 || format_bpb == 2); + logical_el = isl_extent2d(128, 256 / format_bpb); + phys_B = isl_extent2d(128, 32); + break; + default: unreachable("not reached"); } /* end switch */ @@ -231,6 +254,7 @@ isl_surf_choose_tiling(const struct isl_device *dev, CHOOSE(ISL_TILING_LINEAR); } + CHOOSE(ISL_TILING_CCS); CHOOSE(ISL_TILING_HIZ); CHOOSE(ISL_TILING_Ys); CHOOSE(ISL_TILING_Yf); @@ -854,6 +878,29 @@ isl_calc_array_pitch_el_rows(const struct isl_device *dev, assert(pitch_sa_rows % fmtl->bh == 0); uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh; + if (ISL_DEV_GEN(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) { + /* + * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632): + * + * "Mip-mapped and arrayed surfaces are supported with MCS buffer + * layout with these alignments in the RT space: Horizontal + * Alignment = 128 and Vertical Alignment = 64." + * + * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435): + * + * "For non-multisampled render target's CCS auxiliary surface, + * QPitch must be computed with Horizontal Alignment = 128 and + * Surface Vertical Alignment = 256. These alignments are only for + * CCS buffer and not for associated render target." + * + * The first restriction is already handled by isl_choose_image_alignment_el + * but the second restriction, which is an extension of the first, only + * applies to qpitch and must be applied here. + */ + assert(fmtl->bh == 4); + pitch_el_rows = isl_align(pitch_el_rows, 256 / 4); + } + if (ISL_DEV_GEN(dev) >= 9 && info->dim == ISL_SURF_DIM_3D && tile_info->tiling != ISL_TILING_LINEAR) { diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 13882eb2e78..9c036ddc76b 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -356,6 +356,15 @@ enum isl_format { ISL_FORMAT_MCS_4X, ISL_FORMAT_MCS_8X, ISL_FORMAT_MCS_16X, + ISL_FORMAT_GEN7_CCS_32BPP_X, + ISL_FORMAT_GEN7_CCS_64BPP_X, + ISL_FORMAT_GEN7_CCS_128BPP_X, + ISL_FORMAT_GEN7_CCS_32BPP_Y, + ISL_FORMAT_GEN7_CCS_64BPP_Y, + ISL_FORMAT_GEN7_CCS_128BPP_Y, + ISL_FORMAT_GEN9_CCS_32BPP, + ISL_FORMAT_GEN9_CCS_64BPP, + ISL_FORMAT_GEN9_CCS_128BPP, /* Hardware doesn't understand this out-of-band value */ ISL_FORMAT_UNSUPPORTED = UINT16_MAX, @@ -408,6 +417,7 @@ enum isl_txc { /* Used for auxiliary surface formats */ ISL_TXC_HIZ, ISL_TXC_MCS, + ISL_TXC_CCS, }; /** @@ -427,6 +437,7 @@ enum isl_tiling { ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */ ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */ ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */ + ISL_TILING_CCS, /**< Tiling format for CCS surfaces */ }; /** @@ -441,6 +452,7 @@ typedef uint32_t isl_tiling_flags_t; #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf) #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys) #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ) +#define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS) #define ISL_TILING_ANY_MASK (~0u) #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT) @@ -525,6 +537,7 @@ typedef uint64_t isl_surf_usage_flags_t; #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12) #define ISL_SURF_USAGE_HIZ_BIT (1u << 13) #define ISL_SURF_USAGE_MCS_BIT (1u << 14) +#define ISL_SURF_USAGE_CCS_BIT (1u << 15) /** @} */ /** @@ -991,6 +1004,7 @@ isl_format_has_bc_compression(enum isl_format fmt) case ISL_TXC_HIZ: case ISL_TXC_MCS: + case ISL_TXC_CCS: unreachable("Should not be called on an aux surface"); } diff --git a/src/intel/isl/isl_format_layout.csv b/src/intel/isl/isl_format_layout.csv index 972d50f1009..f0f31c72f69 100644 --- a/src/intel/isl/isl_format_layout.csv +++ b/src/intel/isl/isl_format_layout.csv @@ -319,3 +319,12 @@ MCS_2X , 8, 1, 1, 1, , , , , , MCS_4X , 8, 1, 1, 1, , , , , , , , , mcs MCS_8X , 32, 1, 1, 1, , , , , , , , , mcs MCS_16X , 64, 1, 1, 1, , , , , , , , , mcs +GEN7_CCS_32BPP_X , 1, 16, 2, 1, , , , , , , , , ccs +GEN7_CCS_64BPP_X , 1, 8, 2, 1, , , , , , , , , ccs +GEN7_CCS_128BPP_X , 1, 4, 2, 1, , , , , , , , , ccs +GEN7_CCS_32BPP_Y , 1, 8, 4, 1, , , , , , , , , ccs +GEN7_CCS_64BPP_Y , 1, 4, 4, 1, , , , , , , , , ccs +GEN7_CCS_128BPP_Y , 1, 2, 4, 1, , , , , , , , , ccs +GEN9_CCS_32BPP , 2, 8, 4, 1, , , , , , , , , ccs +GEN9_CCS_64BPP , 2, 4, 4, 1, , , , , , , , , ccs +GEN9_CCS_128BPP , 2, 2, 4, 1, , , , , , , , , ccs diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c index bb0ab38bc19..d97d615badd 100644 --- a/src/intel/isl/isl_gen7.c +++ b/src/intel/isl/isl_gen7.c @@ -242,6 +242,13 @@ gen7_filter_tiling(const struct isl_device *dev, if (isl_format_get_layout(info->format)->txc == ISL_TXC_MCS) *flags &= ISL_TILING_Y0_BIT; + /* The CCS formats and tiling always go together */ + if (isl_format_get_layout(info->format)->txc == ISL_TXC_CCS) { + *flags &= ISL_TILING_CCS_BIT; + } else { + *flags &= ~ISL_TILING_CCS_BIT; + } + if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT | ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT | ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) { diff --git a/src/intel/isl/isl_gen8.c b/src/intel/isl/isl_gen8.c index ff35d5f868f..38a759ff08c 100644 --- a/src/intel/isl/isl_gen8.c +++ b/src/intel/isl/isl_gen8.c @@ -204,6 +204,19 @@ gen8_choose_image_alignment_el(const struct isl_device *dev, assert(!isl_tiling_is_std_y(tiling)); + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + if (fmtl->txc == ISL_TXC_CCS) { + /* + * Broadwell PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 676): + * + * "Mip-mapped and arrayed surfaces are supported with MCS buffer + * layout with these alignments in the RT space: Horizontal + * Alignment = 256 and Vertical Alignment = 128. + */ + *image_align_el = isl_extent3d(256 / fmtl->bw, 128 / fmtl->bh, 1); + return; + } + /* The below text from the Broadwell PRM provides some insight into the * hardware's requirements for LOD alignment. From the Broadwell PRM >> * Volume 5: Memory Views >> Surface Layout >> 2D Surfaces: diff --git a/src/intel/isl/isl_gen9.c b/src/intel/isl/isl_gen9.c index ff0dec955a5..9c76ccfc669 100644 --- a/src/intel/isl/isl_gen9.c +++ b/src/intel/isl/isl_gen9.c @@ -106,6 +106,18 @@ gen9_choose_image_alignment_el(const struct isl_device *dev, /* Handled by isl_choose_image_alignment_el */ assert(info->format != ISL_FORMAT_HIZ); + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + if (fmtl->txc == ISL_TXC_CCS) { + /* Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)" (p. 632): + * + * "Mip-mapped and arrayed surfaces are supported with MCS buffer + * layout with these alignments in the RT space: Horizontal + * Alignment = 128 and Vertical Alignment = 64." + */ + *image_align_el = isl_extent3d(128 / fmtl->bw, 64 / fmtl->bh, 1); + return; + } + /* This BSpec text provides some insight into the hardware's alignment * requirements [Skylake BSpec > Memory Views > Common Surface Formats > * Surface Layout and Tiling > 2D Surfaces]: |