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-rw-r--r--src/amd/addrlib/addrinterface.h6
-rw-r--r--src/amd/addrlib/core/addrlib1.cpp19
-rw-r--r--src/amd/addrlib/r800/ciaddrlib.cpp140
-rw-r--r--src/amd/addrlib/r800/ciaddrlib.h7
4 files changed, 152 insertions, 20 deletions
diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h
index c68cacf0952..2a61b2b33f2 100644
--- a/src/amd/addrlib/addrinterface.h
+++ b/src/amd/addrlib/addrinterface.h
@@ -519,7 +519,9 @@ typedef union _ADDR_SURFACE_FLAGS
UINT_32 rotateDisplay : 1; ///< Rotate micro tile type
UINT_32 minimizeAlignment : 1; ///< Minimize alignment
UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode
- UINT_32 reserved : 4; ///< Reserved bits
+ UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface
+ /// to make sure they share same tile config parameters
+ UINT_32 reserved : 3; ///< Reserved bits
};
UINT_32 value;
@@ -628,6 +630,8 @@ typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT
/// Stereo info
ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE
+
+ INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set
} ADDR_COMPUTE_SURFACE_INFO_OUTPUT;
/**
diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp
index 9cdc459867b..fb33145f88d 100644
--- a/src/amd/addrlib/core/addrlib1.cpp
+++ b/src/amd/addrlib/core/addrlib1.cpp
@@ -3557,10 +3557,13 @@ VOID Lib::OptimizeTileMode(
) const
{
AddrTileMode tileMode = pInOut->tileMode;
+
BOOL_32 doOpt = (pInOut->flags.opt4Space == TRUE) ||
(pInOut->flags.minimizeAlignment == TRUE) ||
(pInOut->maxBaseAlign != 0);
+ BOOL_32 convertToPrt = FALSE;
+
// Optimization can only be done on level 0 and samples <= 1
if ((doOpt == TRUE) &&
(pInOut->mipLevel == 0) &&
@@ -3570,7 +3573,6 @@ VOID Lib::OptimizeTileMode(
UINT_32 width = pInOut->width;
UINT_32 height = pInOut->height;
UINT_32 thickness = Thickness(tileMode);
- BOOL_32 convertToPrt = FALSE;
BOOL_32 macroTiledOK = TRUE;
UINT_32 macroWidthAlign = 0;
UINT_32 macroHeightAlign = 0;
@@ -3680,16 +3682,23 @@ VOID Lib::OptimizeTileMode(
}
}
}
+ }
- if (convertToPrt)
+ if (convertToPrt)
+ {
+ if ((pInOut->flags.matchStencilTileCfg == TRUE) && (pInOut->numSamples <= 1))
{
- HwlSetPrtTileMode(pInOut);
+ pInOut->tileMode = ADDR_TM_1D_TILED_THIN1;
}
- else if (tileMode != pInOut->tileMode)
+ else
{
- pInOut->tileMode = tileMode;
+ HwlSetPrtTileMode(pInOut);
}
}
+ else if (tileMode != pInOut->tileMode)
+ {
+ pInOut->tileMode = tileMode;
+ }
HwlOptimizeTileMode(pInOut);
}
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 2c62979619a..5ccc5da4197 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -709,16 +709,60 @@ ADDR_E_RETURNCODE CiLib::HwlComputeSurfaceInfo(
pOut->macroModeIndex = TileIndexInvalid;
}
- // Pass tcCompatible flag from input to output; and turn off it if tile split occurs
- pOut->tcCompatible = pIn->flags.tcCompatible;
-
- ADDR_E_RETURNCODE retCode = SiLib::HwlComputeSurfaceInfo(pIn,pOut);
+ ADDR_E_RETURNCODE retCode = SiLib::HwlComputeSurfaceInfo(pIn, pOut);
if (pOut->macroModeIndex == TileIndexNoMacroIndex)
{
pOut->macroModeIndex = TileIndexInvalid;
}
+ if ((pIn->flags.matchStencilTileCfg == TRUE) &&
+ (pIn->flags.depth == TRUE))
+ {
+ pOut->stencilTileIdx = TileIndexInvalid;
+
+ if ((MinDepth2DThinIndex <= pOut->tileIndex) &&
+ (MaxDepth2DThinIndex >= pOut->tileIndex))
+ {
+ BOOL_32 depthStencil2DTileConfigMatch = DepthStencilTileCfgMatch(pIn, pOut);
+
+ if ((depthStencil2DTileConfigMatch == FALSE) &&
+ (pOut->tcCompatible == TRUE))
+ {
+ pOut->macroModeIndex = TileIndexInvalid;
+
+ ADDR_COMPUTE_SURFACE_INFO_INPUT localIn = *pIn;
+ localIn.tileIndex = TileIndexInvalid;
+ localIn.pTileInfo = NULL;
+ localIn.flags.tcCompatible = FALSE;
+
+ SiLib::HwlComputeSurfaceInfo(&localIn, pOut);
+
+ ADDR_ASSERT((MinDepth2DThinIndex <= pOut->tileIndex) && (MaxDepth2DThinIndex >= pOut->tileIndex));
+
+ depthStencil2DTileConfigMatch = DepthStencilTileCfgMatch(pIn, pOut);
+ }
+
+ if ((depthStencil2DTileConfigMatch == FALSE) &&
+ (pIn->numSamples <= 1))
+ {
+ pOut->macroModeIndex = TileIndexInvalid;
+
+ ADDR_COMPUTE_SURFACE_INFO_INPUT localIn = *pIn;
+ localIn.tileMode = ADDR_TM_1D_TILED_THIN1;
+ localIn.tileIndex = TileIndexInvalid;
+ localIn.pTileInfo = NULL;
+
+ retCode = SiLib::HwlComputeSurfaceInfo(&localIn, pOut);
+ }
+ }
+
+ if (pOut->tileIndex == Depth1DThinIndex)
+ {
+ pOut->stencilTileIdx = Depth1DThinIndex;
+ }
+ }
+
return retCode;
}
@@ -1150,11 +1194,11 @@ VOID CiLib::HwlSelectTileMode(
{
pInOut->flags.opt4Space = TRUE;
pInOut->maxBaseAlign = Block64K;
-
- // Optimize tile mode if possible
- OptimizeTileMode(pInOut);
}
+ // Optimize tile mode if possible
+ OptimizeTileMode(pInOut);
+
HwlOverrideTileMode(pInOut);
}
@@ -1256,6 +1300,12 @@ VOID CiLib::HwlSetupTileInfo(
}
}
+ // tcCompatible flag is only meaningful for gfx8.
+ if (m_settings.isVolcanicIslands == FALSE)
+ {
+ flags.tcCompatible = FALSE;
+ }
+
if (IsTileInfoAllZero(pTileInfo))
{
// See table entries 0-4
@@ -1268,14 +1318,16 @@ VOID CiLib::HwlSetupTileInfo(
if (m_rowSize < tileSize)
{
flags.tcCompatible = FALSE;
- pOut->tcCompatible = FALSE;
}
- if (flags.depth && (flags.nonSplit || flags.tcCompatible || flags.needEquation))
+ if (flags.nonSplit | flags.tcCompatible | flags.needEquation)
{
// Texture readable depth surface should not be split
switch (tileSize)
{
+ case 64:
+ index = 0;
+ break;
case 128:
index = 1;
break;
@@ -1451,7 +1503,7 @@ VOID CiLib::HwlSetupTileInfo(
ADDR_ASSERT(macroTileBytes == PrtTileBytes);
- pOut->tcCompatible = FALSE;
+ flags.tcCompatible = FALSE;
pOut->dccUnsupport = TRUE;
}
}
@@ -1475,7 +1527,6 @@ VOID CiLib::HwlSetupTileInfo(
if (m_rowSize < tileSize)
{
flags.tcCompatible = FALSE;
- pOut->tcCompatible = FALSE;
}
}
@@ -1510,7 +1561,7 @@ VOID CiLib::HwlSetupTileInfo(
*pTileInfo = m_tileTable[8].info;
}
- if (pOut->tcCompatible)
+ if (flags.tcCompatible)
{
if (IsMacroTiled(tileMode))
{
@@ -1535,7 +1586,7 @@ VOID CiLib::HwlSetupTileInfo(
if (m_rowSize < colorTileSplit)
{
- pOut->tcCompatible = FALSE;
+ flags.tcCompatible = FALSE;
}
}
}
@@ -1543,9 +1594,11 @@ VOID CiLib::HwlSetupTileInfo(
else
{
// Client should not enable tc compatible for linear and 1D tile modes.
- pOut->tcCompatible = FALSE;
+ flags.tcCompatible = FALSE;
}
}
+
+ pOut->tcCompatible = flags.tcCompatible;
}
/**
@@ -2177,5 +2230,64 @@ ADDR_E_RETURNCODE CiLib::HwlGetMaxAlignments(
return ADDR_OK;
}
+/**
+****************************************************************************************************
+* CiLib::DepthStencilTileCfgMatch
+*
+* @brief
+* Try to find a tile index for stencil which makes its tile config parameters matches to depth
+* @return
+* TRUE if such tile index for stencil can be found
+****************************************************************************************************
+*/
+BOOL_32 CiLib::DepthStencilTileCfgMatch(
+ const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input structure
+ ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] output structure
+ ) const
+{
+ BOOL_32 depthStencil2DTileConfigMatch = FALSE;
+
+ for (INT_32 stencilTileIndex = MinDepth2DThinIndex;
+ stencilTileIndex <= MaxDepth2DThinIndex;
+ stencilTileIndex++)
+ {
+ ADDR_TILEINFO tileInfo = {0};
+ INT_32 stencilMacroIndex = HwlComputeMacroModeIndex(stencilTileIndex,
+ pIn->flags,
+ 8,
+ pIn->numSamples,
+ &tileInfo);
+
+ if (stencilMacroIndex != TileIndexNoMacroIndex)
+ {
+ if ((m_macroTileTable[stencilMacroIndex].banks ==
+ m_macroTileTable[pOut->macroModeIndex].banks) &&
+ (m_macroTileTable[stencilMacroIndex].bankWidth ==
+ m_macroTileTable[pOut->macroModeIndex].bankWidth) &&
+ (m_macroTileTable[stencilMacroIndex].bankHeight ==
+ m_macroTileTable[pOut->macroModeIndex].bankHeight) &&
+ (m_macroTileTable[stencilMacroIndex].macroAspectRatio ==
+ m_macroTileTable[pOut->macroModeIndex].macroAspectRatio) &&
+ (m_macroTileTable[stencilMacroIndex].pipeConfig ==
+ m_macroTileTable[pOut->macroModeIndex].pipeConfig))
+ {
+ if ((pOut->tcCompatible == FALSE) ||
+ (tileInfo.tileSplitBytes >= MicroTileWidth * MicroTileHeight * pIn->numSamples))
+ {
+ depthStencil2DTileConfigMatch = TRUE;
+ pOut->stencilTileIdx = stencilTileIndex;
+ break;
+ }
+ }
+ }
+ else
+ {
+ ADDR_ASSERT_ALWAYS();
+ }
+ }
+
+ return depthStencil2DTileConfigMatch;
+}
+
} // V1
} // Addr
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 93b2853d066..48835b32822 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -204,8 +204,15 @@ private:
UINT_32 numOfBanks,
UINT_32 numOfSamplesPerSplit) const;
+ BOOL_32 DepthStencilTileCfgMatch(
+ const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
+ ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
+
static const UINT_32 MacroTileTableSize = 16;
static const UINT_32 PrtMacroModeOffset = MacroTileTableSize / 2;
+ static const INT_32 MinDepth2DThinIndex = 0;
+ static const INT_32 MaxDepth2DThinIndex = 4;
+ static const INT_32 Depth1DThinIndex = 5;
ADDR_TILEINFO m_macroTileTable[MacroTileTableSize];
UINT_32 m_noOfMacroEntries;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 02:11:40 +0000