diff options
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 19 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 14 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 2 |
3 files changed, 28 insertions, 7 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index e07a6e7c1fe..6c1ce784269 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -493,6 +493,14 @@ radv_lookup_user_sgpr(struct radv_pipeline *pipeline, gl_shader_stage stage, int idx) { + if (stage == MESA_SHADER_VERTEX) { + if (pipeline->shaders[MESA_SHADER_VERTEX]) + return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx]; + if (pipeline->shaders[MESA_SHADER_TESS_CTRL]) + return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx]; + if (pipeline->shaders[MESA_SHADER_GEOMETRY]) + return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx]; + } return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx]; } @@ -716,9 +724,12 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer, { struct radv_shader_variant *vs; - assert (pipeline->shaders[MESA_SHADER_VERTEX]); + radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en); + /* Skip shaders merged into HS/GS */ vs = pipeline->shaders[MESA_SHADER_VERTEX]; + if (!vs) + return; if (vs->info.vs.as_ls) radv_emit_hw_ls(cmd_buffer, vs); @@ -726,8 +737,6 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer, radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info); else radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo); - - radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en); } @@ -1697,7 +1706,7 @@ radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer) if ((cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline || cmd_buffer->state.vb_dirty) && cmd_buffer->state.pipeline->vertex_elements.count && - cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.has_vertex_buffers) { + radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) { struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements; unsigned vb_offset; void *vb_ptr; @@ -2989,7 +2998,7 @@ radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_cs *cs = cmd_buffer->cs; unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA : V_0287F0_DI_SRC_SEL_AUTO_INDEX; - bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id; + bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id; uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr; assert(base_reg); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 16e4b307e65..4369c3a6b1b 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1207,6 +1207,16 @@ static void si_multiwave_lds_size_workaround(struct radv_device *device, *lds_size = MAX2(*lds_size, 8); } +struct radv_shader_variant * +radv_get_vertex_shader(struct radv_pipeline *pipeline) +{ + if (pipeline->shaders[MESA_SHADER_VERTEX]) + return pipeline->shaders[MESA_SHADER_VERTEX]; + if (pipeline->shaders[MESA_SHADER_TESS_CTRL]) + return pipeline->shaders[MESA_SHADER_TESS_CTRL]; + return pipeline->shaders[MESA_SHADER_GEOMETRY]; +} + static void calculate_tess_state(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) @@ -1223,7 +1233,7 @@ calculate_tess_state(struct radv_pipeline *pipeline, /* This calculates how shader inputs and outputs among VS, TCS, and TES * are laid out in LDS. */ - num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written); + num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written); num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT @@ -2024,7 +2034,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline, if (loc->sgpr_idx != -1) { pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline)); pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4; - if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id) + if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id) pipeline->graphics.vtx_emit_num = 3; else pipeline->graphics.vtx_emit_num = 2; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 2fc64655b1f..0d6431c8c77 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1129,6 +1129,8 @@ struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline, gl_shader_stage stage, int idx); +struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline); + struct radv_graphics_pipeline_create_info { bool use_rectlist; bool db_depth_clear; |