diff options
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 53 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 30 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 2 |
3 files changed, 69 insertions, 16 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 90c7d2639ee..8d04be7295e 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -902,21 +902,44 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, struct radv_color_buffer_info *cb) { bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI; - radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); - radeon_emit(cmd_buffer->cs, cb->cb_color_base); - radeon_emit(cmd_buffer->cs, cb->cb_color_pitch); - radeon_emit(cmd_buffer->cs, cb->cb_color_slice); - radeon_emit(cmd_buffer->cs, cb->cb_color_view); - radeon_emit(cmd_buffer->cs, cb->cb_color_info); - radeon_emit(cmd_buffer->cs, cb->cb_color_attrib); - radeon_emit(cmd_buffer->cs, cb->cb_dcc_control); - radeon_emit(cmd_buffer->cs, cb->cb_color_cmask); - radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice); - radeon_emit(cmd_buffer->cs, cb->cb_color_fmask); - radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice); - - if (is_vi) { /* DCC BASE */ - radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base); + + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); + radeon_emit(cmd_buffer->cs, cb->cb_color_base); + radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32); + radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2); + radeon_emit(cmd_buffer->cs, cb->cb_color_view); + radeon_emit(cmd_buffer->cs, cb->cb_color_info); + radeon_emit(cmd_buffer->cs, cb->cb_color_attrib); + radeon_emit(cmd_buffer->cs, cb->cb_dcc_control); + radeon_emit(cmd_buffer->cs, cb->cb_color_cmask); + radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32); + radeon_emit(cmd_buffer->cs, cb->cb_color_fmask); + radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32); + + radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2); + radeon_emit(cmd_buffer->cs, cb->cb_dcc_base); + radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32); + + radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4, + cb->gfx9_epitch); + } else { + radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); + radeon_emit(cmd_buffer->cs, cb->cb_color_base); + radeon_emit(cmd_buffer->cs, cb->cb_color_pitch); + radeon_emit(cmd_buffer->cs, cb->cb_color_slice); + radeon_emit(cmd_buffer->cs, cb->cb_color_view); + radeon_emit(cmd_buffer->cs, cb->cb_color_info); + radeon_emit(cmd_buffer->cs, cb->cb_color_attrib); + radeon_emit(cmd_buffer->cs, cb->cb_dcc_control); + radeon_emit(cmd_buffer->cs, cb->cb_color_cmask); + radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice); + radeon_emit(cmd_buffer->cs, cb->cb_color_fmask); + radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice); + + if (is_vi) { /* DCC BASE */ + radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base); + } } } diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 59ce2d02a55..8defb736b2c 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -2703,7 +2703,20 @@ radv_initialise_color_surface(struct radv_device *device, va = device->ws->buffer_get_va(iview->bo) + iview->image->offset; - { + if (device->physical_device->rad_info.chip_class >= GFX9) { + struct gfx9_surf_meta_flags meta; + if (iview->image->dcc_offset) + meta = iview->image->surface.u.gfx9.dcc; + else + meta = iview->image->surface.u.gfx9.cmask; + + cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) | + S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) | + S_028C74_RB_ALIGNED(meta.rb_aligned) | + S_028C74_PIPE_ALIGNED(meta.pipe_aligned); + + va += iview->image->surface.u.gfx9.surf_offset >> 8; + } else { const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip]; unsigned pitch_tile_max, slice_tile_max, tile_mode_index; @@ -2835,6 +2848,21 @@ radv_initialise_color_surface(struct radv_device *device, unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh); cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh); } + + if (device->physical_device->rad_info.chip_class >= GFX9) { + uint32_t max_slice = radv_surface_layer_count(iview); + unsigned mip0_depth = iview->base_layer + max_slice - 1; + + cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip); + cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) | + S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type); + cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->image->info.width - 1) | + S_028C68_MIP0_HEIGHT(iview->image->info.height - 1) | + S_028C68_MAX_MIP(iview->image->info.levels); + + cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch); + + } } static void diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 3763e149e57..59b592e42a5 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1342,12 +1342,14 @@ struct radv_color_buffer_info { uint32_t cb_color_view; uint32_t cb_color_info; uint32_t cb_color_attrib; + uint32_t cb_color_attrib2; uint32_t cb_dcc_control; uint32_t cb_color_cmask_slice; uint32_t cb_color_fmask_slice; uint32_t cb_clear_value0; uint32_t cb_clear_value1; uint32_t micro_tile_mode; + uint32_t gfx9_epitch; }; struct radv_ds_buffer_info { |