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-rw-r--r--src/gallium/drivers/radeon/r600_texture.c6
-rw-r--r--src/gallium/drivers/radeon/radeon_winsys.h1
-rw-r--r--src/gallium/drivers/radeonsi/si_blit.c7
-rw-r--r--src/gallium/drivers/radeonsi/si_descriptors.c9
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c2
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_surface.c10
6 files changed, 24 insertions, 11 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 37f8e023c09..b27641722d6 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -72,10 +72,10 @@ bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
* dst: If overwriting the whole texture, discard DCC and use SDMA.
* Otherwise, use the 3D path.
*/
- if (rsrc->dcc_offset)
+ if (rsrc->dcc_offset && rsrc->surface.level[src_level].dcc_enabled)
return false;
- if (rdst->dcc_offset) {
+ if (rdst->dcc_offset && rdst->surface.level[dst_level].dcc_enabled) {
/* We can't discard DCC if the texture has been exported.
* We can only discard DCC for the entire texture.
*/
@@ -1872,7 +1872,7 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
continue;
}
- if (tex->dcc_offset) {
+ if (tex->dcc_offset && tex->surface.level[0].dcc_enabled) {
uint32_t reset_value;
bool clear_words_needed;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index a0c7abf9dc8..d7bb1654a7a 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -360,6 +360,7 @@ struct radeon_surf_level {
uint32_t pitch_bytes;
uint32_t mode;
uint64_t dcc_offset;
+ bool dcc_enabled;
};
struct radeon_surf {
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 34481c1d7ed..2059d9d018c 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -321,6 +321,13 @@ static void si_blit_decompress_color(struct pipe_context *ctx,
if (rtex->dcc_offset && need_dcc_decompress) {
custom_blend = sctx->custom_blend_dcc_decompress;
+
+ /* disable levels without DCC */
+ for (int i = first_level; i <= last_level; i++) {
+ if (!rtex->dcc_offset ||
+ !rtex->surface.level[i].dcc_enabled)
+ level_mask &= ~(1 << i);
+ }
} else if (rtex->fmask.size) {
custom_blend = sctx->custom_blend_decompress;
} else {
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index bb81eb832a9..b2c37135e95 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -331,7 +331,7 @@ void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
is_stencil));
state[4] |= S_008F20_PITCH(pitch - 1);
- if (tex->dcc_offset) {
+ if (tex->dcc_offset && base_level_info->dcc_enabled) {
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = (tex->resource.gpu_address +
tex->dcc_offset +
@@ -591,14 +591,16 @@ static void si_set_shader_image(struct si_context *ctx,
} else {
static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
struct r600_texture *tex = (struct r600_texture *)res;
- unsigned level;
+ unsigned level = view->u.tex.level;
unsigned width, height, depth;
uint32_t *desc = descs->list + slot * 8;
+ bool uses_dcc = tex->dcc_offset &&
+ tex->surface.level[level].dcc_enabled;
assert(!tex->is_depth);
assert(tex->fmask.size == 0);
- if (tex->dcc_offset &&
+ if (uses_dcc &&
view->access & PIPE_IMAGE_ACCESS_WRITE) {
/* If DCC can't be disabled, at least decompress it.
* The decompression is relatively cheap if the surface
@@ -624,7 +626,6 @@ static void si_set_shader_image(struct si_context *ctx,
* selecting a single slice for non-layered bindings
* fails. It doesn't hurt the other targets.
*/
- level = view->u.tex.level;
width = u_minify(res->b.b.width0, level);
height = u_minify(res->b.b.height0, level);
depth = u_minify(res->b.b.depth0, level);
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 9433a2bda27..fc28fc94ebf 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2443,7 +2443,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
}
cb_color_info = cb->cb_color_info | tex->cb_color_info;
- if (tex->dcc_offset)
+ if (tex->dcc_offset && cb->level_info->dcc_enabled)
cb_color_info |= S_028C70_DCC_ENABLE(1);
radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index f609bf43f35..52b3fa88336 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -226,6 +226,10 @@ static int compute_level(struct amdgpu_winsys *ws,
surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
+ /* Clear DCC fields at the beginning. */
+ surf_level->dcc_offset = 0;
+ surf_level->dcc_enabled = false;
+
if (AddrSurfInfoIn->flags.dccCompatible) {
AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
@@ -239,15 +243,14 @@ static int compute_level(struct amdgpu_winsys *ws,
if (ret == ADDR_OK) {
surf_level->dcc_offset = surf->dcc_size;
+ surf_level->dcc_enabled = true;
surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
} else {
surf->dcc_size = 0;
- surf_level->dcc_offset = 0;
}
} else {
surf->dcc_size = 0;
- surf_level->dcc_offset = 0;
}
return 0;
@@ -344,7 +347,8 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
!(surf->flags & RADEON_SURF_SCANOUT) &&
!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
- !compressed && AddrDccIn.numSamples <= 1;
+ !compressed && AddrDccIn.numSamples <= 1 &&
+ surf->last_level == 0;
AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 17:46:48 +0000