diff options
| -rw-r--r-- | src/amd/vulkan/radv_nir_to_llvm.c | 33 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 29 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_shader.h | 1 |
3 files changed, 38 insertions, 25 deletions
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index b175ec386c8..d76969828e3 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -174,6 +174,38 @@ get_tcs_num_patches(struct radv_shader_context *ctx) return num_patches; } +static unsigned +calculate_tess_lds_size(struct radv_shader_context *ctx) +{ + unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices; + unsigned num_tcs_output_cp; + unsigned num_tcs_outputs, num_tcs_patch_outputs; + unsigned input_vertex_size, output_vertex_size; + unsigned input_patch_size, output_patch_size; + unsigned pervertex_output_patch_size; + unsigned output_patch0_offset; + unsigned num_patches; + unsigned lds_size; + + num_tcs_output_cp = ctx->tcs_vertices_per_patch; + num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written); + num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written); + + input_vertex_size = ctx->tcs_num_inputs * 16; + output_vertex_size = num_tcs_outputs * 16; + + input_patch_size = num_tcs_input_cp * input_vertex_size; + + pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size; + output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16; + + num_patches = ctx->tcs_num_patches; + output_patch0_offset = input_patch_size * num_patches; + + lds_size = output_patch0_offset + output_patch_size * num_patches; + return lds_size; +} + /* Tessellation shaders pass outputs to the next shader using LDS. * * LS outputs = TCS inputs @@ -3130,6 +3162,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm, shaders[i]->info.gs.vertices_out; } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) { shader_info->tcs.num_patches = ctx.tcs_num_patches; + shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx); } } diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 771bc2e4080..a4836abf7f1 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1306,38 +1306,17 @@ static struct radv_tessellation_state calculate_tess_state(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) { - unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints; - unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs; - unsigned num_tcs_patch_outputs; - unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size; - unsigned input_patch_size, output_patch_size, output_patch0_offset; + unsigned num_tcs_input_cp; + unsigned num_tcs_output_cp; unsigned lds_size; unsigned num_patches; struct radv_tessellation_state tess = {0}; - /* This calculates how shader inputs and outputs among VS, TCS, and TES - * are laid out in LDS. */ - num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.info.vs.ls_outputs_written); - num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written); //tcs->outputs_written + num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints; num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT - num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.patch_outputs_written); - - /* Ensure that we only need one wave per SIMD so we don't need to check - * resource usage. Also ensures that the number of tcs in and out - * vertices per threadgroup are at most 256. - */ - input_vertex_size = num_tcs_inputs * 16; - output_vertex_size = num_tcs_outputs * 16; - - input_patch_size = num_tcs_input_cp * input_vertex_size; - - pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size; - output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16; - num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; - output_patch0_offset = input_patch_size * num_patches; - lds_size = output_patch0_offset + output_patch_size * num_patches; + lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size; if (pipeline->device->physical_device->rad_info.chip_class >= CIK) { assert(lds_size <= 65536); diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 6066f00c404..45784b8ac43 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -234,6 +234,7 @@ struct radv_shader_variant_info { struct { unsigned tcs_vertices_out; uint32_t num_patches; + uint32_t lds_size; } tcs; struct { struct radv_vs_output_info outinfo; |