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-rw-r--r--src/gallium/drivers/r300/r300_flush.c4
-rw-r--r--src/gallium/drivers/r300/r300_state.c8
2 files changed, 10 insertions, 2 deletions
diff --git a/src/gallium/drivers/r300/r300_flush.c b/src/gallium/drivers/r300/r300_flush.c
index 8b710c1a5ee..9459a95cd73 100644
--- a/src/gallium/drivers/r300/r300_flush.c
+++ b/src/gallium/drivers/r300/r300_flush.c
@@ -72,6 +72,10 @@ void r300_flush(struct pipe_context *pipe,
if (r300->draw && !r300->draw_vbo_locked)
r300_draw_flush_vbuf(r300);
+ if (r300->screen->info.drm_minor >= 12) {
+ flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
+ }
+
if (rfence) {
/* Create a fence, which is a dummy BO. */
*rfence = r300->rws->buffer_create(r300->rws, 1, 1,
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index b0aae534a6d..d704057e466 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -872,8 +872,12 @@ r300_set_framebuffer_state(struct pipe_context* pipe,
r300_mark_atom_dirty(r300, &r300->dsa_state);
}
- /* The tiling flags are dependent on the surface miplevel, unfortunately. */
- r300_fb_set_tiling_flags(r300, state);
+ if (r300->screen->info.drm_minor < 12) {
+ /* The tiling flags are dependent on the surface miplevel, unfortunately.
+ * This workarounds a bad design decision in old kernels which were
+ * rewriting tile fields in registers. */
+ r300_fb_set_tiling_flags(r300, state);
+ }
util_copy_framebuffer_state(r300->fb_state.state, state);