diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_blorp.cpp | 7 |
2 files changed, 11 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 3bf37b9561c..f24fdaf4900 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -1038,13 +1038,16 @@ static void upload_state_base_address( struct brw_context *brw ) */ if (brw->gen >= 6) { + uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + if (brw->gen == 6) intel_emit_post_sync_nonzero_flush(brw); BEGIN_BATCH(10); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); - /* General state base address: stateless DP read/write requests */ - OUT_BATCH(1); + OUT_BATCH(mocs << 8 | /* General State Memory Object Control State */ + mocs << 4 | /* Stateless Data Port Access Memory Object Control State */ + 1); /* General State Base Address Modify Enable */ /* Surface state base address: * BINDING_TABLE_STATE * SURFACE_STATE diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 129c11361a6..b47466abfea 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -74,9 +74,14 @@ void gen6_blorp_emit_state_base_address(struct brw_context *brw, const brw_blorp_params *params) { + uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + BEGIN_BATCH(10); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); - OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */ + OUT_BATCH(mocs << 8 | /* GeneralStateMemoryObjectControlState */ + mocs << 4 | /* StatelessDataPortAccessMemoryObjectControlState */ + 1); /* GeneralStateBaseAddressModifyEnable */ + /* SurfaceStateBaseAddress */ OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1); /* DynamicStateBaseAddress */ |