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-rw-r--r--src/amd/common/ac_surface.c6
-rw-r--r--src/amd/common/ac_surface.h2
-rw-r--r--src/amd/vulkan/radv_image.c2
-rw-r--r--src/gallium/drivers/r600/r600_texture.c4
-rw-r--r--src/gallium/drivers/radeon/radeon_winsys.h1
-rw-r--r--src/gallium/drivers/radeonsi/si_clear.c4
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.h1
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c19
-rw-r--r--src/gallium/drivers/radeonsi/si_texture.c38
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_surface.c3
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_surface.c6
11 files changed, 34 insertions, 52 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 959e7b3d735..afdae1971e9 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -262,7 +262,7 @@ static int surf_config_sanity(const struct ac_surf_config *config,
}
if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) {
- switch (config->info.color_samples) {
+ switch (config->info.storage_samples) {
case 0:
case 1:
case 2:
@@ -694,7 +694,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
AddrDccIn.numSamples = AddrSurfInfoIn.numFrags =
- MAX2(1, config->info.color_samples);
+ MAX2(1, config->info.storage_samples);
}
/* Set the micro tile type. */
@@ -1433,7 +1433,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples;
if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
- AddrSurfInfoIn.numFrags = MAX2(1, config->info.color_samples);
+ AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples);
/* GFX9 doesn't support 1D depth textures, so allocate all 1D textures
* as 2D to avoid having shader variants for 1D vs 2D, so all shaders
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 6d95e610a59..8ba964e64ec 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -226,7 +226,7 @@ struct ac_surf_info {
uint32_t height;
uint32_t depth;
uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */
- uint8_t color_samples; /* For color: color samples */
+ uint8_t storage_samples; /* For color: allocated samples */
uint8_t levels;
uint8_t num_channels; /* heuristic for displayability */
uint16_t array_size;
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 826f898d281..f1c78e8115d 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -937,7 +937,7 @@ radv_image_create(VkDevice _device,
image->info.height = pCreateInfo->extent.height;
image->info.depth = pCreateInfo->extent.depth;
image->info.samples = pCreateInfo->samples;
- image->info.color_samples = pCreateInfo->samples;
+ image->info.storage_samples = pCreateInfo->samples;
image->info.array_size = pCreateInfo->arrayLayers;
image->info.levels = pCreateInfo->mipLevels;
image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 9e2d5c7fc9e..08db6bab04c 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -245,7 +245,7 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
- r = rscreen->ws->surface_init(rscreen->ws, ptex, ptex->nr_samples,
+ r = rscreen->ws->surface_init(rscreen->ws, ptex,
flags, bpe, array_mode, surface);
if (r) {
return r;
@@ -616,7 +616,7 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
bpe *= 2;
}
- if (rscreen->ws->surface_init(rscreen->ws, &templ, templ.nr_samples,
+ if (rscreen->ws->surface_init(rscreen->ws, &templ,
flags, bpe, RADEON_SURF_MODE_2D, &fmask)) {
R600_ERR("Got error in surface_init while allocating FMASK.\n");
return;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 406cfe46da3..99a793f9028 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -643,7 +643,6 @@ struct radeon_winsys {
*/
int (*surface_init)(struct radeon_winsys *ws,
const struct pipe_resource *tex,
- unsigned num_color_samples,
unsigned flags, unsigned bpe,
enum radeon_surf_mode mode,
struct radeon_surf *surf);
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index e614ab52423..4e07de81bac 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -237,7 +237,7 @@ void vi_dcc_clear_level(struct si_context *sctx,
assert(tex->buffer.b.b.last_level == 0);
/* 4x and 8x MSAA needs a sophisticated compute shader for
* the clear. See AMDVLK. */
- assert(tex->num_color_samples <= 2);
+ assert(tex->buffer.b.b.nr_storage_samples <= 2);
clear_size = tex->surface.dcc_size;
} else {
unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
@@ -248,7 +248,7 @@ void vi_dcc_clear_level(struct si_context *sctx,
* dcc_fast_clear_size bytes for each layer. A compute shader
* would be more efficient than separate per-layer clear operations.
*/
- assert(tex->num_color_samples <= 2 || num_layers == 1);
+ assert(tex->buffer.b.b.nr_storage_samples <= 2 || num_layers == 1);
dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 4a3e8bba18e..9ab79bcaa2e 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -248,7 +248,6 @@ struct si_texture {
unsigned color_clear_value[2];
unsigned last_msaa_resolve_target_micro_mode;
unsigned num_level0_transfers;
- unsigned num_color_samples;
/* Depth buffer compression and fast clear. */
uint64_t htile_offset;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index fc5d63f02d3..a1b00cb979a 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2431,7 +2431,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
if (tex->buffer.b.b.nr_samples > 1) {
unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
- unsigned log_fragments = util_logbase2(tex->num_color_samples);
+ unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
S_028C74_NUM_FRAGMENTS(log_fragments);
@@ -2458,7 +2458,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
if (!sctx->screen->info.has_dedicated_vram)
min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
- if (tex->num_color_samples > 1) {
+ if (tex->buffer.b.b.nr_storage_samples > 1) {
if (tex->surface.bpe == 1)
max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
else if (tex->surface.bpe == 2)
@@ -2869,10 +2869,12 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
* (e.g. destination of MSAA resolve)
*/
if (tex->buffer.b.b.nr_samples >= 2 &&
- tex->num_color_samples < tex->buffer.b.b.nr_samples) {
+ tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
sctx->framebuffer.nr_color_samples =
MIN2(sctx->framebuffer.nr_color_samples,
- tex->num_color_samples);
+ tex->buffer.b.b.nr_storage_samples);
+ sctx->framebuffer.nr_color_samples =
+ MAX2(1, sctx->framebuffer.nr_color_samples);
}
if (tex->surface.is_linear)
@@ -3633,7 +3635,8 @@ si_make_texture_descriptor(struct si_screen *screen,
desc = util_format_description(pipe_format);
num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
- MAX2(1, res->nr_samples) : tex->num_color_samples;
+ MAX2(1, res->nr_samples) :
+ MAX2(1, res->nr_storage_samples);
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
@@ -3831,10 +3834,10 @@ si_make_texture_descriptor(struct si_screen *screen,
va = tex->buffer.gpu_address + tex->fmask_offset;
-#define FMASK(s,f) (((unsigned)(s) * 16) + (f))
+#define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
if (screen->info.chip_class >= GFX9) {
data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
- switch (FMASK(res->nr_samples, tex->num_color_samples)) {
+ switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
case FMASK(2,1):
num_format = V_008F14_IMG_FMASK_8_2_1;
break;
@@ -3878,7 +3881,7 @@ si_make_texture_descriptor(struct si_screen *screen,
unreachable("invalid nr_samples");
}
} else {
- switch (FMASK(res->nr_samples, tex->num_color_samples)) {
+ switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
case FMASK(2,1):
data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
break;
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 46df4aecf09..e55fd815264 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -220,7 +220,6 @@ static unsigned si_texture_get_offset(struct si_screen *sscreen,
static int si_init_surface(struct si_screen *sscreen,
struct radeon_surf *surface,
const struct pipe_resource *ptex,
- unsigned num_color_samples,
enum radeon_surf_mode array_mode,
unsigned pitch_in_bytes_override,
unsigned offset,
@@ -280,13 +279,13 @@ static int si_init_surface(struct si_screen *sscreen,
/* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
if (sscreen->info.chip_class == VI &&
- num_color_samples >= 4 &&
+ ptex->nr_storage_samples >= 4 &&
ptex->array_size > 1)
flags |= RADEON_SURF_DISABLE_DCC;
/* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
if (sscreen->info.chip_class >= GFX9 &&
- num_color_samples >= 4)
+ ptex->nr_storage_samples >= 4)
flags |= RADEON_SURF_DISABLE_DCC;
if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
@@ -307,8 +306,8 @@ static int si_init_surface(struct si_screen *sscreen,
if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_TILING))
flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
- r = sscreen->ws->surface_init(sscreen->ws, ptex, num_color_samples,
- flags, bpe, array_mode, surface);
+ r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe,
+ array_mode, surface);
if (r) {
return r;
}
@@ -1114,7 +1113,6 @@ void si_print_texture_info(struct si_screen *sscreen,
static struct si_texture *
si_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
- unsigned num_color_samples,
struct pb_buffer *buf,
struct radeon_surf *surface)
{
@@ -1138,7 +1136,6 @@ si_texture_create_object(struct pipe_screen *screen,
tex->surface = *surface;
tex->size = tex->surface.surf_size;
- tex->num_color_samples = num_color_samples;
tex->tc_compatible_htile = tex->surface.htile_size != 0 &&
(tex->surface.flags &
@@ -1358,17 +1355,6 @@ si_choose_tiling(struct si_screen *sscreen,
return RADEON_SURF_MODE_2D;
}
-static unsigned si_get_num_color_samples(struct si_screen *sscreen,
- const struct pipe_resource *templ,
- bool imported)
-{
- if (!imported && templ->nr_samples >= 2 &&
- sscreen->eqaa_force_color_samples)
- return sscreen->eqaa_force_color_samples;
-
- return CLAMP(templ->nr_samples, 1, 8);
-}
-
struct pipe_resource *si_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
@@ -1382,10 +1368,13 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
*/
if (is_zs && sscreen->eqaa_force_z_samples) {
((struct pipe_resource*)templ)->nr_samples =
+ ((struct pipe_resource*)templ)->nr_storage_samples =
sscreen->eqaa_force_z_samples;
} else if (!is_zs && sscreen->eqaa_force_color_samples) {
((struct pipe_resource*)templ)->nr_samples =
sscreen->eqaa_force_coverage_samples;
+ ((struct pipe_resource*)templ)->nr_storage_samples =
+ sscreen->eqaa_force_color_samples;
}
}
@@ -1405,10 +1394,9 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
!is_flushed_depth &&
templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient with MSAA */
is_zs;
- unsigned num_color_samples = si_get_num_color_samples(sscreen, templ, false);
int r;
- r = si_init_surface(sscreen, &surface, templ, num_color_samples,
+ r = si_init_surface(sscreen, &surface, templ,
si_choose_tiling(sscreen, templ, tc_compatible_htile),
0, 0, false, false, is_flushed_depth,
tc_compatible_htile);
@@ -1417,8 +1405,7 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
}
return (struct pipe_resource *)
- si_texture_create_object(screen, templ, num_color_samples,
- NULL, &surface);
+ si_texture_create_object(screen, templ, NULL, &surface);
}
static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *sscreen,
@@ -1467,16 +1454,13 @@ static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *ssc
is_scanout = false;
}
- unsigned num_color_samples = si_get_num_color_samples(sscreen, templ, true);
-
- r = si_init_surface(sscreen, &surface, templ, num_color_samples,
+ r = si_init_surface(sscreen, &surface, templ,
array_mode, stride, offset, true, is_scanout,
false, false);
if (r)
return NULL;
- tex = si_texture_create_object(&sscreen->b, templ, num_color_samples,
- buf, &surface);
+ tex = si_texture_create_object(&sscreen->b, templ, buf, &surface);
if (!tex)
return NULL;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index eaf10349355..2f0d0f28fc1 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -62,7 +62,6 @@ static int amdgpu_surface_sanity(const struct pipe_resource *tex)
static int amdgpu_surface_init(struct radeon_winsys *rws,
const struct pipe_resource *tex,
- unsigned num_color_samples,
unsigned flags, unsigned bpe,
enum radeon_surf_mode mode,
struct radeon_surf *surf)
@@ -86,7 +85,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
config.info.depth = tex->depth0;
config.info.array_size = tex->array_size;
config.info.samples = tex->nr_samples;
- config.info.color_samples = num_color_samples;
+ config.info.storage_samples = tex->nr_storage_samples;
config.info.levels = tex->last_level + 1;
config.info.num_channels = util_format_get_nr_components(tex->format);
config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index d528a6fe638..fda1ba7870e 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -282,7 +282,6 @@ static void si_compute_cmask(const struct radeon_info *info,
static int radeon_winsys_surface_init(struct radeon_winsys *rws,
const struct pipe_resource *tex,
- unsigned num_color_samples,
unsigned flags, unsigned bpe,
enum radeon_surf_mode mode,
struct radeon_surf *surf_ws)
@@ -330,9 +329,8 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws,
return -1;
}
- if (radeon_winsys_surface_init(rws, &templ, num_color_samples,
- fmask_flags, bpe, RADEON_SURF_MODE_2D,
- &fmask)) {
+ if (radeon_winsys_surface_init(rws, &templ, fmask_flags, bpe,
+ RADEON_SURF_MODE_2D, &fmask)) {
fprintf(stderr, "Got error in surface_init while allocating FMASK.\n");
return -1;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-16 14:59:49 +0000