diff options
| -rw-r--r-- | src/intel/compiler/brw_eu_emit.c | 16 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs_generator.cpp | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_shader.cpp | 2 |
3 files changed, 20 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 4f0be550983..e10b1432b5e 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -3373,6 +3373,8 @@ brw_broadcast(struct brw_codegen *p, assert(src.file == BRW_GENERAL_REGISTER_FILE && src.address_mode == BRW_ADDRESS_DIRECT); + assert(!src.abs && !src.negate); + assert(src.type == dst.type); if ((src.vstride == 0 && (src.hstride == 0 || !align1)) || idx.file == BRW_IMMEDIATE_VALUE) { @@ -3385,6 +3387,20 @@ brw_broadcast(struct brw_codegen *p, (align1 ? stride(suboffset(src, i), 0, 1, 0) : stride(suboffset(src, 4 * i), 0, 4, 1))); } else { + /* From the Haswell PRM section "Register Region Restrictions": + * + * "The lower bits of the AddressImmediate must not overflow to + * change the register address. The lower 5 bits of Address + * Immediate when added to lower 5 bits of address register gives + * the sub-register offset. The upper bits of Address Immediate + * when added to upper bits of address register gives the register + * address. Any overflow from sub-register offset is dropped." + * + * Fortunately, for broadcast, we never have a sub-register offset so + * this isn't an issue. + */ + assert(src.subnr == 0); + if (align1) { const struct brw_reg addr = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD); diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index f9ea4eaedeb..09bd6dbeb40 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -445,6 +445,8 @@ fs_generator::generate_mov_indirect(fs_inst *inst, { assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD); assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE); + assert(!reg.abs && !reg.negate); + assert(reg.type == dst.type); unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr; diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index fe230cd7cc2..971ff4f608c 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -851,6 +851,8 @@ backend_instruction::can_do_source_mods() const case BRW_OPCODE_FBH: case BRW_OPCODE_FBL: case BRW_OPCODE_SUBB: + case SHADER_OPCODE_BROADCAST: + case SHADER_OPCODE_MOV_INDIRECT: return false; default: return true; |