diff options
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp | 26 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/AMDILTargetMachine.cpp | 10 |
2 files changed, 18 insertions, 18 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp index 313349ce01b..4357d198bbe 100644 --- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp +++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp @@ -112,31 +112,31 @@ AMDGPUPassConfig::addPreISel() { const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>(); if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) { - PM.add(createR600KernelParametersPass( + PM->add(createR600KernelParametersPass( getAMDGPUTargetMachine().getTargetData())); } return false; } bool AMDGPUPassConfig::addInstSelector() { - PM.add(createAMDILPeepholeOpt(*TM)); - PM.add(createAMDILISelDag(getAMDGPUTargetMachine())); + PM->add(createAMDILPeepholeOpt(*TM)); + PM->add(createAMDILISelDag(getAMDGPUTargetMachine())); return false; } bool AMDGPUPassConfig::addPreRegAlloc() { const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>(); - PM.add(createAMDGPUReorderPreloadInstructionsPass(*TM)); + PM->add(createAMDGPUReorderPreloadInstructionsPass(*TM)); if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) { - PM.add(createR600LowerShaderInstructionsPass(*TM)); - PM.add(createR600LowerInstructionsPass(*TM)); + PM->add(createR600LowerShaderInstructionsPass(*TM)); + PM->add(createR600LowerInstructionsPass(*TM)); } else { - PM.add(createSILowerShaderInstructionsPass(*TM)); - PM.add(createSIAssignInterpRegsPass(*TM)); + PM->add(createSILowerShaderInstructionsPass(*TM)); + PM->add(createSIAssignInterpRegsPass(*TM)); } - PM.add(createAMDGPULowerInstructionsPass(*TM)); - PM.add(createAMDGPUConvertToISAPass(*TM)); + PM->add(createAMDGPULowerInstructionsPass(*TM)); + PM->add(createAMDGPUConvertToISAPass(*TM)); return false; } @@ -150,10 +150,10 @@ bool AMDGPUPassConfig::addPreSched2() { bool AMDGPUPassConfig::addPreEmitPass() { const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>(); - PM.add(createAMDILCFGPreparationPass(*TM)); - PM.add(createAMDILCFGStructurizerPass(*TM)); + PM->add(createAMDILCFGPreparationPass(*TM)); + PM->add(createAMDILCFGStructurizerPass(*TM)); if (ST.device()->getGeneration() == AMDILDeviceInfo::HD7XXX) { - PM.add(createSIPropagateImmReadsPass(*TM)); + PM->add(createSIPropagateImmReadsPass(*TM)); } return false; diff --git a/src/gallium/drivers/radeon/AMDILTargetMachine.cpp b/src/gallium/drivers/radeon/AMDILTargetMachine.cpp index 77fac1d97bd..0879d43ad72 100644 --- a/src/gallium/drivers/radeon/AMDILTargetMachine.cpp +++ b/src/gallium/drivers/radeon/AMDILTargetMachine.cpp @@ -150,8 +150,8 @@ bool AMDILPassConfig::addPreISel() bool AMDILPassConfig::addInstSelector() { - PM.add(createAMDILPeepholeOpt(*TM)); - PM.add(createAMDILISelDag(getAMDILTargetMachine())); + PM->add(createAMDILPeepholeOpt(*TM)); + PM->add(createAMDILISelDag(getAMDILTargetMachine())); return false; } @@ -162,7 +162,7 @@ bool AMDILPassConfig::addPreRegAlloc() llvm::RegisterScheduler::setDefault(&llvm::createSourceListDAGScheduler); } - PM.add(createAMDILMachinePeephole(*TM)); + PM->add(createAMDILMachinePeephole(*TM)); return false; } @@ -175,8 +175,8 @@ bool AMDILPassConfig::addPostRegAlloc() { /// true if -print-machineinstrs should print out the code after the passes. bool AMDILPassConfig::addPreEmitPass() { - PM.add(createAMDILCFGPreparationPass(*TM)); - PM.add(createAMDILCFGStructurizerPass(*TM)); + PM->add(createAMDILCFGPreparationPass(*TM)); + PM->add(createAMDILCFGStructurizerPass(*TM)); return true; } |