diff options
| -rw-r--r-- | src/intel/blorp/blorp_genX_exec.h | 3 | ||||
| -rw-r--r-- | src/intel/compiler/brw_compiler.h | 7 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs_visitor.cpp | 1 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_pipeline.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen4_blorp_exec.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/genX_state_upload.c | 2 |
6 files changed, 15 insertions, 1 deletions
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index d2eba276f87..13bdd851e94 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -765,6 +765,7 @@ blorp_emit_ps_config(struct blorp_batch *batch, if (prog_data) { ps._8PixelDispatchEnable = prog_data->dispatch_8; ps._16PixelDispatchEnable = prog_data->dispatch_16; + ps._32PixelDispatchEnable = prog_data->dispatch_32; ps.DispatchGRFStartRegisterForConstantSetupData0 = brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0); @@ -874,6 +875,7 @@ blorp_emit_ps_config(struct blorp_batch *batch, if (prog_data) { ps._8PixelDispatchEnable = prog_data->dispatch_8; ps._16PixelDispatchEnable = prog_data->dispatch_16; + ps._32PixelDispatchEnable = prog_data->dispatch_32; ps.DispatchGRFStartRegisterForConstantSetupData0 = brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0); @@ -941,6 +943,7 @@ blorp_emit_ps_config(struct blorp_batch *batch, wm._8PixelDispatchEnable = prog_data->dispatch_8; wm._16PixelDispatchEnable = prog_data->dispatch_16; + wm._32PixelDispatchEnable = prog_data->dispatch_32; wm.DispatchGRFStartRegisterForConstantSetupData0 = brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm, 0); diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 1b9589c231a..2f745d92745 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -685,9 +685,12 @@ struct brw_wm_prog_data { uint8_t reg_blocks_8; uint8_t reg_blocks_16; + uint8_t reg_blocks_32; uint8_t dispatch_grf_start_reg_16; + uint8_t dispatch_grf_start_reg_32; uint32_t prog_offset_16; + uint32_t prog_offset_32; struct { /** @{ @@ -705,6 +708,7 @@ struct brw_wm_prog_data { bool inner_coverage; bool dispatch_8; bool dispatch_16; + bool dispatch_32; bool dual_src_blend; bool persample_dispatch; bool uses_pos_offset; @@ -789,6 +793,7 @@ _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data *prog_data, switch (simd_width) { case 8: return 0; case 16: return prog_data->prog_offset_16; + case 32: return prog_data->prog_offset_32; default: return 0; } } @@ -804,6 +809,7 @@ _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data *prog_dat switch (simd_width) { case 8: return prog_data->base.dispatch_grf_start_reg; case 16: return prog_data->dispatch_grf_start_reg_16; + case 32: return prog_data->dispatch_grf_start_reg_32; default: return 0; } } @@ -819,6 +825,7 @@ _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data *prog_data, switch (simd_width) { case 8: return prog_data->reg_blocks_8; case 16: return prog_data->reg_blocks_16; + case 32: return prog_data->reg_blocks_32; default: return 0; } } diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index 5459b1ea276..0ca230e888c 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -127,6 +127,7 @@ fs_visitor::emit_dummy_fs() stage_prog_data->curb_read_length = 0; stage_prog_data->dispatch_grf_start_reg = 2; wm_prog_data->dispatch_grf_start_reg_16 = 2; + wm_prog_data->dispatch_grf_start_reg_32 = 2; grf_used = 1; /* Gen4-5 don't allow zero GRF blocks */ calculate_cfg(); diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 80165b81d3b..15b1e0b3880 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -1490,7 +1490,7 @@ emit_3dstate_ps(struct anv_pipeline *pipeline, anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) { ps._8PixelDispatchEnable = wm_prog_data->dispatch_8; ps._16PixelDispatchEnable = wm_prog_data->dispatch_16; - ps._32PixelDispatchEnable = false; + ps._32PixelDispatchEnable = wm_prog_data->dispatch_32; ps.KernelStartPointer0 = fs_bin->kernel.offset + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 0); diff --git a/src/mesa/drivers/dri/i965/gen4_blorp_exec.h b/src/mesa/drivers/dri/i965/gen4_blorp_exec.h index e3b90f12d96..0edc518fa35 100644 --- a/src/mesa/drivers/dri/i965/gen4_blorp_exec.h +++ b/src/mesa/drivers/dri/i965/gen4_blorp_exec.h @@ -132,6 +132,7 @@ blorp_emit_wm_state(struct blorp_batch *batch, wm._8PixelDispatchEnable = prog_data->dispatch_8; wm._16PixelDispatchEnable = prog_data->dispatch_16; + wm._32PixelDispatchEnable = prog_data->dispatch_32; #if GEN_GEN == 4 wm.KernelStartPointer0 = diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index 189245d91f9..42cd08ceba9 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -1895,6 +1895,7 @@ genX(upload_wm)(struct brw_context *brw) #if GEN_GEN <= 6 wm._8PixelDispatchEnable = wm_prog_data->dispatch_8; wm._16PixelDispatchEnable = wm_prog_data->dispatch_16; + wm._32PixelDispatchEnable = wm_prog_data->dispatch_32; #endif #if GEN_GEN == 4 @@ -4029,6 +4030,7 @@ genX(upload_ps)(struct brw_context *brw) ps._8PixelDispatchEnable = prog_data->dispatch_8; ps._16PixelDispatchEnable = prog_data->dispatch_16; + ps._32PixelDispatchEnable = prog_data->dispatch_32; ps.DispatchGRFStartRegisterForConstantSetupData0 = brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0); |