diff options
| -rw-r--r-- | src/intel/isl/isl.h | 9 | ||||
| -rw-r--r-- | src/intel/isl/isl_surface_state.c | 18 |
2 files changed, 23 insertions, 4 deletions
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 2edf0522e32..c50b78d4701 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -1308,6 +1308,15 @@ struct isl_surf_fill_state_info { union isl_color_value clear_color; /** + * Send only the clear value address + * + * If set, we only pass the clear address to the GPU and it will fetch it + * from wherever it is. + */ + bool use_clear_address; + uint64_t clear_address; + + /** * Surface write disables for gen4-5 */ isl_channel_mask_t write_disables; diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 32a5429f2bf..bff9693f02d 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -637,11 +637,21 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif if (info->aux_usage != ISL_AUX_USAGE_NONE) { + if (info->use_clear_address) { +#if GEN_GEN >= 10 + s.ClearValueAddressEnable = true; + s.ClearValueAddress = info->clear_address; +#else + unreachable("Gen9 and earlier do not support indirect clear colors"); +#endif + } #if GEN_GEN >= 9 - s.RedClearColor = info->clear_color.u32[0]; - s.GreenClearColor = info->clear_color.u32[1]; - s.BlueClearColor = info->clear_color.u32[2]; - s.AlphaClearColor = info->clear_color.u32[3]; + if (!info->use_clear_address) { + s.RedClearColor = info->clear_color.u32[0]; + s.GreenClearColor = info->clear_color.u32[1]; + s.BlueClearColor = info->clear_color.u32[2]; + s.AlphaClearColor = info->clear_color.u32[3]; + } #elif GEN_GEN >= 7 /* Prior to Sky Lake, we only have one bit for the clear color which * gives us 0 or 1 in whatever the surface's format happens to be. |