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-rw-r--r--src/intel/vulkan/anv_pipeline.c14
-rw-r--r--src/intel/vulkan/genX_pipeline.c2
2 files changed, 13 insertions, 3 deletions
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 87788de10a5..8f30136b100 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -1247,8 +1247,18 @@ anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
if (subpass && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
assert(info->pDepthStencilState);
- if (subpass && subpass->color_count > 0)
- assert(info->pColorBlendState);
+ if (subpass && subpass->color_count > 0) {
+ bool all_color_unused = true;
+ for (int i = 0; i < subpass->color_count; i++) {
+ if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
+ all_color_unused = false;
+ }
+ /* pColorBlendState is ignored if the pipeline has rasterization
+ * disabled or if the subpass of the render pass the pipeline is
+ * created against does not use any color attachments.
+ */
+ assert(info->pColorBlendState || all_color_unused);
+ }
}
for (uint32_t i = 0; i < info->stageCount; ++i) {
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index d3af9304ba3..6016d257584 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1361,7 +1361,7 @@ has_color_buffer_write_enabled(const struct anv_pipeline *pipeline,
if (binding->index == UINT32_MAX)
continue;
- if (blend->pAttachments[binding->index].colorWriteMask != 0)
+ if (blend && blend->pAttachments[binding->index].colorWriteMask != 0)
return true;
}