diff options
| -rw-r--r-- | src/intel/isl/isl.c | 14 | ||||
| -rw-r--r-- | src/intel/isl/isl_surface_state.c | 11 | ||||
| -rw-r--r-- | src/intel/vulkan/anv_meta_blit2d.c | 2 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 7 |
4 files changed, 15 insertions, 19 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index c710bca6d29..4205c1c03a4 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -133,10 +133,20 @@ isl_tiling_get_info(const struct isl_device *dev, break; case ISL_TILING_W: - /* XXX: Should W tile be same as Y? */ assert(bs == 1); logical_el = isl_extent2d(64, 64); - phys_B = isl_extent2d(64, 64); + /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch: + * + * "If the surface is a stencil buffer (and thus has Tile Mode set + * to TILEMODE_WMAJOR), the pitch must be set to 2x the value + * computed based on width, as the stencil buffer is stored with two + * rows interleaved." + * + * This, together with the fact that stencil buffers are referred to as + * being Y-tiled in the PRMs for older hardware implies that the + * physical size of a W-tile is actually the same as for a Y-tile. + */ + phys_B = isl_extent2d(128, 32); break; case ISL_TILING_Yf: diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index b2317d81bdc..c65126db880 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -298,16 +298,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height]; s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width]; - if (info->surf->tiling == ISL_TILING_W) { - /* From the Broadwell PRM documentation for this field: - * - * "If the surface is a stencil buffer (and thus has Tile Mode set - * to TILEMODE_WMAJOR), the pitch must be set to 2x the value - * computed based on width, as the stencil buffer is stored with - * two rows interleaved." - */ - s.SurfacePitch = info->surf->row_pitch * 2 - 1; - } else if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { + if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { /* For gen9 1-D textures, surface pitch is ignored */ s.SurfacePitch = 0; } else { diff --git a/src/intel/vulkan/anv_meta_blit2d.c b/src/intel/vulkan/anv_meta_blit2d.c index 06e10432952..d37d69d96b7 100644 --- a/src/intel/vulkan/anv_meta_blit2d.c +++ b/src/intel/vulkan/anv_meta_blit2d.c @@ -540,7 +540,7 @@ anv_meta_blit2d_w_tiled_dst(struct anv_cmd_buffer *cmd_buffer, .tiling = ISL_TILING_Y0, .base_offset = dst->base_offset, .bs = 1, - .pitch = dst->pitch * 2, + .pitch = dst->pitch, }; struct blit2d_dst_temps dst_temps; diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index ed90a91499f..648649fbb93 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1112,12 +1112,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer) #endif sb.StencilBufferObjectControlState = GENX(MOCS), - /* Stencil buffers have strange pitch. The PRM says: - * - * The pitch must be set to 2x the value computed based on width, - * as the stencil buffer is stored with two rows interleaved. - */ - sb.SurfacePitch = 2 * image->stencil_surface.isl.row_pitch - 1, + sb.SurfacePitch = image->stencil_surface.isl.row_pitch - 1, #if GEN_GEN >= 8 sb.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->stencil_surface.isl) >> 2, |