diff options
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 4 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_get.c | 5 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 36 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 2 |
5 files changed, 26 insertions, 23 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 68750b2db28..7678a18b355 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -320,6 +320,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->htile_cmask_support_1d_tiling = true; info->si_TA_CS_BC_BASE_ADDR_allowed = true; info->has_bo_metadata = true; + info->has_gpu_reset_status_query = true; + info->has_gpu_reset_counter_query = false; info->num_render_backends = amdinfo->rb_pipes; /* The value returned by the kernel driver was wrong. */ @@ -471,6 +473,8 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling); printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed); printf(" has_bo_metadata = %u\n", info->has_bo_metadata); + printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query); + printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query); printf("Shader core info:\n"); printf(" max_shader_clock = %i\n", info->max_shader_clock); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 340c368bda3..f5b74579ef1 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -100,6 +100,8 @@ struct radeon_info { bool htile_cmask_support_1d_tiling; bool si_TA_CS_BC_BASE_ADDR_allowed; bool has_bo_metadata; + bool has_gpu_reset_status_query; + bool has_gpu_reset_counter_query; /* Shader cores. */ uint32_t r600_max_quad_pipes; /* wave size / 16 */ diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index c31ab43cb42..cd3e63c73d7 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -203,9 +203,8 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return !SI_BIG_ENDIAN && sscreen->info.has_userptr; case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: - return (sscreen->info.drm_major == 2 && - sscreen->info.drm_minor >= 43) || - sscreen->info.drm_major == 3; + return sscreen->info.has_gpu_reset_status_query || + sscreen->info.has_gpu_reset_counter_query; case PIPE_CAP_TEXTURE_MULTISAMPLE: /* 2D tiling on CIK is supported since DRM 2.35.0 */ diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index d5ca34474f0..bf61b0071e7 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -286,25 +286,25 @@ static void si_destroy_context(struct pipe_context *context) FREE(sctx); } -static enum pipe_reset_status -si_amdgpu_get_reset_status(struct pipe_context *ctx) +static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx) { struct si_context *sctx = (struct si_context *)ctx; - return sctx->ws->ctx_query_reset_status(sctx->ctx); -} + if (sctx->screen->info.has_gpu_reset_status_query) + return sctx->ws->ctx_query_reset_status(sctx->ctx); -static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx) -{ - struct si_context *sctx = (struct si_context *)ctx; - unsigned latest = sctx->ws->query_value(sctx->ws, - RADEON_GPU_RESET_COUNTER); + if (sctx->screen->info.has_gpu_reset_counter_query) { + unsigned latest = sctx->ws->query_value(sctx->ws, + RADEON_GPU_RESET_COUNTER); + + if (sctx->gpu_reset_counter == latest) + return PIPE_NO_RESET; - if (sctx->gpu_reset_counter == latest) - return PIPE_NO_RESET; + sctx->gpu_reset_counter = latest; + return PIPE_UNKNOWN_CONTEXT_RESET; + } - sctx->gpu_reset_counter = latest; - return PIPE_UNKNOWN_CONTEXT_RESET; + return PIPE_NO_RESET; } static void si_set_device_reset_callback(struct pipe_context *ctx, @@ -411,13 +411,12 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, sctx->family = sscreen->info.family; sctx->chip_class = sscreen->info.chip_class; - if (sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 43) { - sctx->b.get_device_reset_status = si_get_reset_status; + if (sscreen->info.has_gpu_reset_counter_query) { sctx->gpu_reset_counter = - sctx->ws->query_value(sctx->ws, - RADEON_GPU_RESET_COUNTER); + sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER); } + sctx->b.get_device_reset_status = si_get_reset_status; sctx->b.set_device_reset_callback = si_set_device_reset_callback; si_init_context_texture_functions(sctx); @@ -468,9 +467,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, sctx); } - if (sscreen->info.drm_major == 3) - sctx->b.get_device_reset_status = si_amdgpu_get_reset_status; - si_init_buffer_functions(sctx); si_init_clear_functions(sctx); si_init_blit_functions(sctx); diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index d7ecfe9f240..7189b61ef11 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -534,6 +534,8 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->info.drm_minor >= 38; ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48; ws->info.has_bo_metadata = false; + ws->info.has_gpu_reset_status_query = false; + ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43; ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; |