diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 4 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index ace83ef57af..312dddafd77 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1609,6 +1609,7 @@ enum brw_pixel_shader_coverage_mask_mode { #define GEN7_GPGPU_DISPATCHDIMZ 0x2508 #define GEN7_CACHE_MODE_1 0x7004 +# define GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4) # define GEN8_HIZ_NP_PMA_FIX_ENABLE (1 << 11) # define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13) # define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index bcb7ff1231e..4647f1c41e0 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -65,7 +65,9 @@ brw_upload_initial_gpu_state(struct brw_context *brw) BEGIN_BATCH(3); OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); OUT_BATCH(GEN7_CACHE_MODE_1); - OUT_BATCH(REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) | + OUT_BATCH(REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) | + REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) | + GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE | GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC); ADVANCE_BATCH(); } |