diff options
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_compute.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/a5xx/fd5_draw.h | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/freedreno/adreno_pm4.xml.h | 277 |
3 files changed, 171 insertions, 114 deletions
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c index 55cddadf600..f9fb599e785 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c @@ -165,9 +165,9 @@ fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) OUT_PKT7(ring, CP_EXEC_CS_INDIRECT, 4); OUT_RING(ring, 0x00000000); OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */ - OUT_RING(ring, CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) | - CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) | - CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1)); + OUT_RING(ring, A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) | + A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) | + A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1)); } else { OUT_PKT7(ring, CP_EXEC_CS, 4); OUT_RING(ring, 0x00000000); diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_draw.h b/src/gallium/drivers/freedreno/a5xx/fd5_draw.h index e33085fcd5b..d1069157e75 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_draw.h +++ b/src/gallium/drivers/freedreno/a5xx/fd5_draw.h @@ -105,7 +105,7 @@ fd5_draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring, &batch->draw_patches); OUT_RELOC(ring, fd_resource(idx)->bo, index_offset, 0, 0); - OUT_RING(ring, CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies)); + OUT_RING(ring, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies)); OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0); } else { OUT_PKT7(ring, CP_DRAW_INDIRECT, 3); diff --git a/src/gallium/drivers/freedreno/adreno_pm4.xml.h b/src/gallium/drivers/freedreno/adreno_pm4.xml.h index 99404e8c0c9..d6f49e7ccfa 100644 --- a/src/gallium/drivers/freedreno/adreno_pm4.xml.h +++ b/src/gallium/drivers/freedreno/adreno_pm4.xml.h @@ -8,15 +8,15 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 33379 bytes, from 2017-11-14 21:00:47) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 143420 bytes, from 2017-11-16 20:29:34) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27) +- /home/ilia/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-11-18 20:43:22) +- /home/ilia/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-11 01:04:14) +- /home/ilia/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2017-11-18 20:48:10) +- /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 15292 bytes, from 2017-11-19 20:45:26) +- /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34349 bytes, from 2017-11-19 20:43:33) +- /home/ilia/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-11-18 19:40:11) +- /home/ilia/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112609 bytes, from 2017-11-19 04:47:10) +- /home/ilia/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 143017 bytes, from 2017-11-19 04:05:11) +- /home/ilia/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-11-07 21:10:25) Copyright (C) 2013-2017 by the following authors: - Rob Clark <[email protected]> (robclark) @@ -583,124 +583,151 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; } -#define REG_CP_DRAW_INDIRECT_0 0x00000000 -#define CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f -#define CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0 -static inline uint32_t CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) +#define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000 +#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f +#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0 +static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) { - return ((val) << CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK; + return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK; } -#define CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 -#define CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6 -static inline uint32_t CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) +#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 +#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6 +static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) { - return ((val) << CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK; + return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK; } -#define CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300 -#define CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8 -static inline uint32_t CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) +#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300 +#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8 +static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) { - return ((val) << CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & CP_DRAW_INDIRECT_0_VIS_CULL__MASK; + return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK; } -#define CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 -#define CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10 -static inline uint32_t CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) +#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 +#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10 +static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) { - return ((val) << CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK; + return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK; } -#define CP_DRAW_INDIRECT_0_TESS_MODE__MASK 0x01f00000 -#define CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT 20 -static inline uint32_t CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val) +#define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK 0x01f00000 +#define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT 20 +static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val) { - return ((val) << CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & CP_DRAW_INDIRECT_0_TESS_MODE__MASK; + return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK; } -#define REG_CP_DRAW_INDIRECT_1 0x00000001 -#define CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff -#define CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0 -static inline uint32_t CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val) +#define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001 +#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff +#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0 +static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) { - return ((val) << CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK; + return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK; } -#define REG_CP_DRAW_INDIRECT_2 0x00000002 -#define CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff -#define CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0 -static inline uint32_t CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val) + +#define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002 +#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff +#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0 +static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val) { - return ((val) << CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK; + return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK; } -#define REG_CP_DRAW_INDX_INDIRECT_0 0x00000000 -#define CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f -#define CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) +#define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000 +#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f +#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0 +static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) +{ + return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK; +} +#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 +#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6 +static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) +{ + return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK; +} +#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300 +#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8 +static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) +{ + return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK; +} +#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 +#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10 +static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) { - return ((val) << CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK; + return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK; } -#define CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 -#define CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6 -static inline uint32_t CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) +#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK 0x01f00000 +#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT 20 +static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val) { - return ((val) << CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK; + return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK; } -#define CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300 -#define CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8 -static inline uint32_t CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) + + +#define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 +#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff +#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0 +static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val) { - return ((val) << CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK; + return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK; } -#define CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 -#define CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10 -static inline uint32_t CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) + +#define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 +#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff +#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0 +static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val) { - return ((val) << CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK; + return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK; } -#define CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK 0x01f00000 -#define CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT 20 -static inline uint32_t CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val) + +#define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 +#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff +#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0 +static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) { - return ((val) << CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK; + return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK; } -#define REG_CP_DRAW_INDX_INDIRECT_1 0x00000001 -#define CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff -#define CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val) + +#define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 +#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff +#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0 +static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val) { - return ((val) << CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK; + return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK; } -#define REG_CP_DRAW_INDX_INDIRECT_2 0x00000002 -#define CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff -#define CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val) +#define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 +#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff +#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0 +static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val) { - return ((val) << CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK; + return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK; } -#define REG_CP_DRAW_INDX_INDIRECT_3 0x00000003 -#define CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff -#define CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val) +#define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 +#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff +#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0 +static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val) { - return ((val) << CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK; + return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK; } -#define REG_CP_DRAW_INDX_INDIRECT_4 0x00000004 -#define CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff -#define CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val) +#define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004 +#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff +#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0 +static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val) { - return ((val) << CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK; + return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK; } -#define REG_CP_DRAW_INDX_INDIRECT_5 0x00000005 -#define CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff -#define CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val) +#define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005 +#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff +#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0 +static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val) { - return ((val) << CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK; + return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK; } static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } @@ -1236,42 +1263,72 @@ static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK; } -#define REG_CP_EXEC_CS_INDIRECT_0 0x00000000 +#define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000 + + +#define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001 +#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff +#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0 +static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val) +{ + return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK; +} + +#define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002 +#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc +#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2 +static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val) +{ + return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK; +} +#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000 +#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12 +static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val) +{ + return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK; +} +#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000 +#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22 +static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) +{ + return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK; +} + -#define REG_CP_EXEC_CS_INDIRECT_1 0x00000001 -#define CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff -#define CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0 -static inline uint32_t CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val) +#define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001 +#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff +#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0 +static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val) { - return ((val) << CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK; + return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK; } -#define REG_CP_EXEC_CS_INDIRECT_2 0x00000002 -#define CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff -#define CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0 -static inline uint32_t CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val) +#define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002 +#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff +#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0 +static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val) { - return ((val) << CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK; + return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK; } -#define REG_CP_EXEC_CS_INDIRECT_3 0x00000003 -#define CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc -#define CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2 -static inline uint32_t CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val) +#define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003 +#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc +#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2 +static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val) { - return ((val) << CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK; + return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK; } -#define CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000 -#define CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12 -static inline uint32_t CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val) +#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000 +#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12 +static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val) { - return ((val) << CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK; + return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK; } -#define CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000 -#define CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22 -static inline uint32_t CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val) +#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000 +#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22 +static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val) { - return ((val) << CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK; + return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK; } |